[U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board

Heiko Schocher hs at denx.de
Fri Sep 30 10:46:55 CEST 2011


Hello Christian,

Christian Riesch wrote:
> Hello Heiko,
> 
> On Mon, Sep 19, 2011 at 7:50 AM, Heiko Schocher <hs at denx.de> wrote:
>> - booting from NOR Flash with direct boot method
>> - POST support
>> - LOGBUF support
>>
>> Signed-off-by: Heiko Schocher <hs at denx.de>
>> Cc: Paulraj Sandeep <s-paulraj at ti.com>
>> Cc: Albert ARIBAUD <albert.u.boot at aribaud.net>
>> Cc: Igor Grinberg <grinberg at compulab.co.il>
>> ---
>> - changes for v2
>>  - use CONFIG_MACH_TYPE instead setting the MACH_TYPE in
>>    board specific code, as Igor Grinberg suggested.
>>  - add logversion=2 to default Environment
>>
>>  board/enbw/enbw_cmc/Makefile   |   51 ++++
>>  board/enbw/enbw_cmc/enbw_cmc.c |  570 ++++++++++++++++++++++++++++++++++++++++
>>  boards.cfg                     |    1 +
>>  include/configs/enbw_cmc.h     |  443 +++++++++++++++++++++++++++++++
>>  4 files changed, 1065 insertions(+), 0 deletions(-)
>>  create mode 100644 board/enbw/enbw_cmc/Makefile
>>  create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
>>  create mode 100644 include/configs/enbw_cmc.h
> 
> [...]
> 
>> diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
>> new file mode 100644
>> index 0000000..e203089
>> --- /dev/null
>> +++ b/include/configs/enbw_cmc.h
> 
> [...]
> 
>> +#define CONFIG_SYS_AM1808_PLL0_PLLM    37      /* PLL0 -> 456 MHz */
> 
> With a 24 MHz input frequency this would result in a PLL0 frequency of
> 24MHz / PREDIV * (CONFIG_SYS_AM1808_PLL0_PLLM + 1), so I guess you
> assume a PREDIV of 2 here (PREDIV register value 0x00008001). However,

No. The comment is wrong! I fix the comment from PLL0 to PLLC0
in the next patch version, thanks!

> the AM1808 datasheet and the reference guide (section 7.3.10) state
> that the default PREDIV is 1 (register value 0x00008000) and I don't
> see how you set the PREDIV to 2. Am I missing something here?

For calculating the resulting frequencies for the used Sysclocks
don;t forget the POSTDIV value

#define CONFIG_SYS_AM1808_PLL0_POSTDIV  1

So the correct calculation is:

(24MHz / PREDIV * (CONFIG_SYS_AM1808_PLL0_PLLM + 1)) / POSTDIV

(And with that, I get 456 MHz ;-)

bye,
Heiko
-- 
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