[U-Boot] [PATCH 1/2]ARM: EXYNOS: add mipi dsi control operation
Donghwa Lee
dh09.lee at samsung.com
Wed Apr 4 08:29:04 CEST 2012
To control mipi dsi interface for EXYNOS SoC, base register address, device
clock and any others control register must be set up.
This patch sets up above control operation.
[PATCH v3 1/4] ARM: EXYNOS: definition of system registers
[PATCH v3 3/4] ARM: EXYNOS: add exynos lcd clock interface
Signed-off-by: Donghwa Lee <dh09.lee at samsung.com>
Signed-off-by: Inki Dae <inki.dae at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
arch/arm/cpu/armv7/exynos/Makefile | 2 +-
arch/arm/cpu/armv7/exynos/clock.c | 34 +++++++++++++++++++++
arch/arm/cpu/armv7/exynos/power.c | 47 ++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-exynos/clk.h | 1 +
arch/arm/include/asm/arch-exynos/cpu.h | 3 ++
arch/arm/include/asm/arch-exynos/power.h | 6 ++++
6 files changed, 92 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/armv7/exynos/power.c
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
index 75c31dc..90ec2bd 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS += clock.o soc.o system.o
+COBJS += clock.o power.o soc.o system.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index ecaa11e..e4735a3 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -479,6 +479,34 @@ void exynos4_set_lcd_clk(void)
writel(cfg, &clk->div_lcd0);
}
+void exynos4_set_mipi_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned int cfg = 0;
+
+ /* set mipi0 src clock 0x6: SCLK_MPLL */
+ cfg = readl(&clk->src_lcd0);
+ cfg &= ~(0xf << 12);
+ cfg |= (0x6 << 12);
+ writel(cfg, &clk->src_lcd0);
+
+ /* set src mask mipi0 0x1: Unmask*/
+ cfg = readl(&clk->src_mask_lcd0);
+ cfg |= (0x1 << 12);
+ writel(cfg, &clk->src_mask_lcd0);
+
+ /* Gating all clocks for MIPI0 */
+ cfg = readl(&clk->gate_ip_lcd0);
+ cfg |= 1 << 3;
+ writel(cfg, &clk->gate_ip_lcd0);
+
+ /* set fimd ratio */
+ cfg &= ~(0xf << 16);
+ cfg |= (0x1 << 16);
+ writel(cfg, &clk->div_lcd0);
+}
+
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5())
@@ -532,3 +560,9 @@ void set_lcd_clk(void)
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
}
+
+void set_mipi_clk(void)
+{
+ if (cpu_is_exynos4())
+ exynos4_set_mipi_clk();
+}
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
new file mode 100644
index 0000000..cbd91ef
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/power.h>
+
+static void exynos4_mipi_phy0_control(int enable, unsigned int reset)
+{
+ struct exynos4_power *pmu =
+ (struct exynos4_power *)samsung_get_base_power();
+ unsigned int cfg = 0;
+
+ cfg = readl(&pmu->mipi_phy0_control);
+ if (enable)
+ cfg |= (reset | EXYNOS_MIPI_PHY_ENABLE);
+ else
+ cfg &= ~(reset | EXYNOS_MIPI_PHY_ENABLE);
+
+ writel(cfg, &pmu->mipi_phy0_control);
+}
+
+void set_mipi_phy0_ctrl(int enable, unsigned int reset)
+{
+ if (cpu_is_exynos4())
+ exynos4_mipi_phy0_control(enable, reset);
+}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index cf00dea..637fb4b 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -35,5 +35,6 @@ unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
unsigned long get_lcd_clk(void);
void set_lcd_clk(void);
+void set_mipi_clk(void);
#endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 70048f0..ac4ddc7 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -41,6 +41,7 @@
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
+#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4_USBOTG_BASE 0x12480000
#define EXYNOS4_MMC_BASE 0x12510000
#define EXYNOS4_SROMC_BASE 0x12570000
@@ -66,6 +67,7 @@
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
+#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
#define EXYNOS5_MMC_BASE 0x12200000
#define EXYNOS5_SROMC_BASE 0x12250000
#define EXYNOS5_USBOTG_BASE 0x12480000
@@ -130,6 +132,7 @@ SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index fb442f7..393d4ac 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -227,4 +227,10 @@ struct exynos4_power {
};
#endif /* __ASSEMBLY__ */
+void set_mipi_phy0_ctrl(int enable, unsigned int reset);
+
+#define EXYNOS_MIPI_PHY_ENABLE (1 << 0)
+#define EXYNOS_MIPI_PHY_SRESETN (1 << 1)
+#define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
+
#endif
--
1.7.4.1
More information about the U-Boot
mailing list