[U-Boot] PCI Resource allocation for Cavium MIPS board

[Wolfgang Denk]

Dear Sudhanshu B,

In message <loom.20120406T115130-656 at post.gmane.org> you wrote:
> 
> I am working on Cavium MIPS 5860 Series board, PCI Initialization sequence in
> uboot seems to be OK, as per Hardware manual. There are two FPGA devices which
> are connected on BUS 0, however i am unable to read my PCI memory space.
> I think PCI BAR 0 mapping has some problems. I am able to config space,
> vendor,class etc., but not able to read any of the target register.
> 
> Current code implementation only recognizes both of my PCI devices, however i am
> unable to see the correct BAR0 address.
> 
> My requirement is to correctly allocate the resources (BAR0 memory) for PCI
> devices in uboot.

Please contact Cavium support about this.  They never pushed their
code into mainline, so we cannot help you.

Best regards,

Wolfgang Denk

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