[U-Boot] [PATCH] davinci/spi: allow usage of other chip selects and buses

[Jérôme Carretero]

Use the spi_slave bus and cs attributes, reduce C2T/T2C delays,
allow overriding of spi_cs_is_valid().

As it is, this patch breaks the configuration files for DaVinci boards
that only use SPI1.

Signed-off-by: Jérôme Carretero <cJ at zougloub.eu>
CC: Manjunathappa, Prakash <prakash.pm at ti.com>
--
 drivers/spi/davinci_spi.c |   16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 13aca52..74f385e 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -23,6 +23,9 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
+ * References: SPRUH77 Chapter 30
+ *
  */
 #include <common.h>
 #include <spi.h>
@@ -50,7 +53,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 	ds->slave.bus = bus;
 	ds->slave.cs = cs;
-	ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE;
+	ds->regs = (struct davinci_spi_regs *)(bus == 0 ? DAVINCI_SPI0_BASE : DAVINCI_SPI1_BASE);
 	ds->freq = max_hz;
 
 	return &ds->slave;
@@ -67,6 +70,7 @@ int spi_claim_bus(struct spi_slave *slave)
 {
 	struct davinci_spi_slave *ds = to_davinci_spi(slave);
 	unsigned int scalar;
+	unsigned int cs;
 
 	/* Enable the SPI hardware */
 	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
@@ -76,8 +80,9 @@ int spi_claim_bus(struct spi_slave *slave)
 	/* Set master mode, powered up and not activated */
 	writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
 
+	cs = BIT(slave->cs); /* SPIPC0_EN0FUN_MASK ... */
 	/* CS, CLK, SIMO and SOMI are functional pins */
-	writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK |
+	writel((cs | SPIPC0_CLKFUN_MASK |
 		SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
 
 	/* setup format */
@@ -97,11 +102,11 @@ int spi_claim_bus(struct spi_slave *slave)
 	 * Including a minor delay. No science here. Should be good even with
 	 * no delay
 	 */
-	writel((50 << SPI_C2TDELAY_SHIFT) |
-		(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
+	writel((10 << SPI_C2TDELAY_SHIFT) |
+		(10 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
 
 	/* default chip select register */
-	writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
+	writel(cs, &ds->regs->def);
 
 	/* no interrupts */
 	writel(0, &ds->regs->int0);
@@ -280,6 +285,7 @@ out:
 	return 0;
 }
 
+__attribute__((weak))
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
 	return bus == 0 && cs == 0;
-- 
1.7.9.4