[U-Boot] [PATCH] i.MX2: Support splash screen

Timo Ketola timo at exertus.fi
Wed Apr 18 10:54:21 CEST 2012


Signed-off-by: Timo Ketola <timo at exertus.fi>
---
 arch/arm/include/asm/arch-mx25/imx-regs.h |   29 +++++++++
 drivers/video/Makefile                    |    1 +
 drivers/video/mx2fb.c                     |   92 +++++++++++++++++++++++++++++
 include/lcd.h                             |   21 ++++++-
 include/mx2fb.h                           |   39 ++++++++++++
 5 files changed, 181 insertions(+), 1 deletions(-)
 create mode 100644 drivers/video/mx2fb.c
 create mode 100644 include/mx2fb.h

diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 7f9449b..af5b42e 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -167,6 +167,35 @@ struct aips_regs {
 	u32 mpr_8_15;
 };
 
+struct lcdc_regs {
+	u32 lssar;
+	u32 lsr;
+	u32 lvpwr;
+	u32 lcpr;
+	u32 lcwhb;
+	u32 lccmr;
+	u32 lpcr;
+	u32 lhcr;
+	u32 lvcr;
+	u32 lpor;
+	u32 lscr;
+	u32 lpccr;
+	u32 ldcr;
+	u32 lrmcr;
+	u32 licr;
+	u32 lier;
+	u32 lisr;
+	u32 pad0[3];
+	u32 lgwsar;
+	u32 lgwsr;
+	u32 lgwvpwr;
+	u32 lgwpor;
+	u32 lgwpr;
+	u32 pad1[0x200 - 25];
+	u32 bglut[0x100];
+	u32 gwlut[0x100];
+};
+
 #endif
 
 /* AIPS 1 */
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6252f6a..e047471 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -36,6 +36,7 @@ COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
 COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
+COBJS-$(CONFIG_VIDEO_MX2) += mx2fb.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
 COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o videomodes.o
diff --git a/drivers/video/mx2fb.c b/drivers/video/mx2fb.c
new file mode 100644
index 0000000..9ee4a3e
--- /dev/null
+++ b/drivers/video/mx2fb.c
@@ -0,0 +1,92 @@
+#include <common.h>
+#include <lcd.h>
+#include <mx2fb.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#if !defined(LCD_BPP) || LCD_BPP != LCD_COLOR16
+
+#error Only 16bpp is supported
+
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base;			/* Start of framebuffer memory	*/
+void *lcd_console_address;	/* Start of console buffer	*/
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	u32 ccm_ipg_cg, pcr;
+	struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE;
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+
+	writel(gd->fb_base, &lcdc->lssar);
+	writel(panel_info.vl_col >> 4 << 20 | panel_info.vl_row, &lcdc->lsr);
+	writel(panel_info.vl_col / 2, &lcdc->lvpwr);
+	if (panel_info.vl_bpix != 4)
+		printf("Unsupported color depth (%d), only 16bpp supported\n",
+				NBITS(panel_info.vl_bpix));
+	pcr = LCDC_LPCR | 5 << 25;
+
+	if (panel_info.vl_sync & FB_SYNC_CLK_LAT_FALL)
+		pcr |= 0x00200000;
+	if (panel_info.vl_sync & FB_SYNC_DATA_INVERT)
+		pcr |= 0x01000000;
+	if (panel_info.vl_sync & FB_SYNC_SHARP_MODE)
+		pcr |= 0x00000040;
+	if (panel_info.vl_sync & FB_SYNC_OE_LOW_ACT)
+		pcr |= 0x00100000;
+
+	pcr |= LCDC_LPCR_PCD;
+
+	writel(pcr, &lcdc->lpcr);
+	writel((panel_info.vl_hsync - 1) << 26 |
+				(panel_info.vl_right_margin - 1) << 8 |
+				(panel_info.vl_left_margin - 3),
+			&lcdc->lhcr);
+	writel(panel_info.vl_vsync << 26 |
+				panel_info.vl_lower_margin << 8 |
+				panel_info.vl_upper_margin,
+			&lcdc->lvcr);
+	writel(LCDC_LSCR, &lcdc->lscr);
+	writel(LCDC_LRMCR, &lcdc->lrmcr);
+	writel(LCDC_LDCR, &lcdc->ldcr);
+	writel(LCDC_LPCCR, &lcdc->lpccr);
+
+	/* Off and on clock gating
+	   FIXME: Why *off* and on; What side effects does it have? */
+	ccm_ipg_cg = readl(&ccm->cgr1);
+
+	writel(ccm_ipg_cg & 0xDFFFFFFF, &ccm->cgr1);
+	writel(ccm_ipg_cg | 0x20000000, &ccm->cgr1);
+}
diff --git a/include/lcd.h b/include/lcd.h
index d95feeb..a5eeb53 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -183,6 +183,25 @@ typedef struct vidinfo {
 	u_long	mmio;		/* Memory mapped registers */
 } vidinfo_t;
 
+#elif defined(CONFIG_VIDEO_MX2)
+
+struct vidinfo {
+	ushort vl_row;		/* resolution in x */
+	ushort vl_col;		/* resolution in y */
+	u_long vl_pixclock;	/* pixel clock in picoseconds */
+	u_long vl_left_margin;	/* Horizontal back porch */
+	u_long vl_right_margin; /* Horizontal front porch */
+	u_long vl_upper_margin; /* Vertical back porch */
+	u_long vl_lower_margin; /* Vertical front porch */
+	u_long vl_hsync;	/* Horizontal sync pulse length */
+	u_long vl_vsync;	/* Vertical sync pulse length */
+	u_long vl_sync;		/* Polarity on data enable */
+	u_long vl_mode;		/* Video Mode */
+	u_long vl_flag;
+	u_char vl_bpix;
+	ushort *cmap;
+};
+
 #else
 
 typedef struct vidinfo {
@@ -198,7 +217,7 @@ typedef struct vidinfo {
 
 #endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
 
-extern vidinfo_t panel_info;
+extern struct vidinfo panel_info;
 
 /* Video functions */
 
diff --git a/include/mx2fb.h b/include/mx2fb.h
new file mode 100644
index 0000000..1f16a61
--- /dev/null
+++ b/include/mx2fb.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MX2FB_H__
+#define __MX2FB_H__
+
+
+/* LCDC register settings */
+
+#define LCDC_LSCR 0x00120300
+
+#define LCDC_LRMCR 0x00000000
+
+#define LCDC_LDCR 0x00020010
+
+#define LCDC_LPCCR 0x00a9037f
+
+#define LCDC_LPCR 0xFA008B80
+
+#define LCDC_LPCR_PCD 0x4
+
+#define FB_SYNC_OE_LOW_ACT	0x80000000
+#define FB_SYNC_CLK_LAT_FALL	0x40000000
+#define FB_SYNC_DATA_INVERT	0x20000000
+#define FB_SYNC_CLK_IDLE_EN	0x10000000
+#define FB_SYNC_SHARP_MODE	0x08000000
+#define FB_SYNC_SWAP_RGB	0x04000000
+
+#endif
-- 
1.7.5.4



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