[U-Boot] [PATCH 4/4][v3] powerpc/85xx:Fix NAND code base to support debugger
Prabhakar Kushwaha
prabhakar at freescale.com
Mon Apr 30 11:56:56 CEST 2012
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.
As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data
Signed-off-by: Radu Lazarescu <radu.lazarescu at freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
Based upon git://git.denx.de/u-boot.git branch master
Changes for v2:
- Removed unnecessary CONFIG_E500
- Avoid TLB creation for NAND_SPL
Changes for v3:
- Moved IVPR code out of CONFIG_NAND_SPL
- Placed this code to patch 3.
Tested on
- SoC having E500 Family processor (P1010RDB, BSC9131RDB)
- SoC having E500MC Family processor (P4080DS, P3041DS)
arch/powerpc/cpu/mpc85xx/start.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 858d391..930f639 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -182,7 +182,7 @@ l2_disabled:
andi. r1,r3,L1CSR0_DCE at l
beq 2b
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
--
1.7.5.4
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