[U-Boot] [PATCH] powerpc/p2041: configure the CPLD lane_mux according to RCW

[Andy Fleming]

On Fri, Jun 29, 2012 at 4:37 AM, Shaohui Xie <Shaohui.Xie at freescale.com> wrote:
> Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
> is 0xc, CPLD supports SATA by default, we should re-configure the lane
> muxing according to RCW, which indicates what SerDes protocol it is running.
>
> Default lane muxing map is as below:
> Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
> Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
> Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
> and bit 3 respectively.
>
> Default value of these bits for lane muxing is '1', we should set or clear
> these bits accoring to RCW.
>
> Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
> Acked-by: Timur Tabi <timur at freescale.com>

Applied, thanks