[U-Boot] [PATCH 2/5] MSM 7x27a: Add support for qualcomm msm 7x27a SOC
Srikanth Reddy Vintha
srikanth.reddy at lntinfotech.com
Mon Aug 13 10:20:43 CEST 2012
Signed-off-by: Srikanth Reddy Vintha <srikanth.reddy at lntinfotech.com>
---
arch/arm/cpu/armv7/msm7x27a/Makefile | 53 ++++
arch/arm/cpu/armv7/msm7x27a/acpuclock.c | 252 +++++++++++++++
arch/arm/cpu/armv7/msm7x27a/board.c | 66 ++++
arch/arm/cpu/armv7/msm7x27a/config.mk | 21 ++
arch/arm/cpu/armv7/msm7x27a/gpio.c | 287 +++++++++++++++++
arch/arm/cpu/armv7/msm7x27a/lowlevel_init.S | 118 +++++++
arch/arm/cpu/armv7/msm7x27a/timer.c | 127 ++++++++
arch/arm/include/asm/arch-msm7x27a/gpio.h | 47 +++
arch/arm/include/asm/arch-msm7x27a/iomap.h | 105 +++++++
arch/arm/include/asm/arch-msm7x27a/mmc.h | 399 ++++++++++++++++++++++++
arch/arm/include/asm/arch-msm7x27a/proc_comm.h | 42 +++
arch/arm/include/asm/arch-msm7x27a/sys_proto.h | 27 ++
12 files changed, 1544 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/msm7x27a/Makefile
create mode 100644 arch/arm/cpu/armv7/msm7x27a/acpuclock.c
create mode 100644 arch/arm/cpu/armv7/msm7x27a/board.c
create mode 100644 arch/arm/cpu/armv7/msm7x27a/config.mk
create mode 100644 arch/arm/cpu/armv7/msm7x27a/gpio.c
create mode 100644 arch/arm/cpu/armv7/msm7x27a/lowlevel_init.S
create mode 100644 arch/arm/cpu/armv7/msm7x27a/timer.c
create mode 100644 arch/arm/include/asm/arch-msm7x27a/gpio.h
create mode 100644 arch/arm/include/asm/arch-msm7x27a/iomap.h
create mode 100644 arch/arm/include/asm/arch-msm7x27a/mmc.h
create mode 100644 arch/arm/include/asm/arch-msm7x27a/proc_comm.h
create mode 100644 arch/arm/include/asm/arch-msm7x27a/sys_proto.h
diff --git a/arch/arm/cpu/armv7/msm7x27a/Makefile b/arch/arm/cpu/armv7/msm7x27a/Makefile
new file mode 100644
index 0000000..5f493d7
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7x27a/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2012
+# Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS-y := lowlevel_init.o
+COBJS-y := board.o
+COBJS-y += timer.o
+COBJS-y += acpuclock.o
+COBJS-y += gpio.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
new file mode 100644
index 0000000..c144233
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
@@ -0,0 +1,252 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
+ *
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <asm/arch/iomap.h>
+#include <asm/io.h>
+#include <common.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/proc_comm.h>
+
+#define BIT(x) (1 << (x))
+
+#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
+#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
+#define VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
+
+#define PLL2_MODE_ADDR (MSM_CLK_CTL_BASE + 0x338)
+#define PLL4_MODE_ADDR (MSM_CLK_CTL_BASE + 0x374)
+
+#define PLL_RESET_N BIT(2)
+#define PLL_BYPASSNL BIT(1)
+#define PLL_OUTCTRL BIT(0)
+
+#define SRC_SEL_TCX0 0 /* TCXO */
+#define SRC_SEL_PLL1 1 /* PLL1: modem_pll */
+#define SRC_SEL_PLL2 2 /* PLL2: backup_pll_0 */
+#define SRC_SEL_PLL3 3 /* PLL3: backup_pll_1 */
+#define SRC_SEL_PLL4 6 /* PLL4: sparrow_pll */
+
+#define DIV_1 0
+#define DIV_2 1
+#define DIV_3 2
+#define DIV_4 3
+#define DIV_5 4
+#define DIV_6 5
+#define DIV_7 6
+#define DIV_8 7
+#define DIV_9 8
+#define DIV_10 9
+#define DIV_11 10
+#define DIV_12 11
+#define DIV_13 12
+#define DIV_14 13
+#define DIV_15 14
+#define DIV_16 15
+
+#define WAIT_CNT 100
+#define VDD_LEVEL 7
+#define MIN_AXI_HZ 120000000
+#define ACPU_800MHZ 41
+
+#define A11S_CLK_SEL_MASK 0x7 /* bits 2:0 */
+
+/* The stepping frequencies have been choosen to make sure the step
+ * is <= 256 MHz for both 7x27a and 7x25a targets. The
+ * table also assumes the ACPU is running at TCXO freq and AHB div is
+ * set to DIV_1.
+ *
+ * To use the tables:
+ * - Start at location 0/1 depending on clock source sel bit.
+ * - Set values till end of table skipping every other entry.
+ * - When you reach the end of the table, you are done scaling.
+ */
+
+uint32_t const clk_cntl_reg_val_7627A[] = {
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8),
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
+
+ /* TODO: Fix it for 800MHz */
+#if 0
+ (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_1,
+#endif
+};
+
+
+/* Using DIV_1 for all cases to avoid worrying about turbo vs. normal
+ * mode. Able to use DIV_1 for all steps because it's the largest AND
+ * the final value. */
+uint32_t const clk_sel_reg_val[] = {
+ DIV_1 << 1 | 1, /* Switch to src1 */
+ DIV_1 << 1 | 0, /* Switch to src0 */
+};
+
+/*
+ * Mask to make sure current selected src frequency doesn't change.
+ */
+uint32_t const clk_cntl_mask[] = {
+ 0x0000FF00, /* Mask to read src0 */
+ 0x000000FF /* Mask to read src1 */
+};
+
+/* enum for SDC CLK IDs */
+enum {
+ SDC1_CLK = 19,
+ SDC1_PCLK = 20,
+ SDC2_CLK = 21,
+ SDC2_PCLK = 22,
+ SDC3_CLK = 23,
+ SDC3_PCLK = 24,
+ SDC4_CLK = 25,
+ SDC4_PCLK = 26
+};
+static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
+static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
+
+
+void pll_enable(void *pll_mode_addr)
+{
+ uint32_t nVal;
+ /* Check status */
+ nVal = readl(pll_mode_addr);
+ if (nVal & PLL_OUTCTRL)
+ return;
+
+ /* Put the PLL in reset mode */
+ nVal = 0;
+ nVal &= ~PLL_RESET_N;
+ nVal &= ~PLL_BYPASSNL;
+ nVal &= ~PLL_OUTCTRL;
+ writel(nVal, pll_mode_addr);
+
+ /* Put the PLL in warm-up mode */
+ nVal |= PLL_RESET_N;
+ nVal |= PLL_BYPASSNL;
+ writel(nVal, pll_mode_addr);
+
+ /* Wait for the PLL warm-up time */
+ udelay(50);
+
+ /* Put the PLL in active mode */
+ nVal |= PLL_RESET_N;
+ nVal |= PLL_BYPASSNL;
+ nVal |= PLL_OUTCTRL;
+ writel(nVal, pll_mode_addr);
+}
+
+void pll_request(unsigned pll, unsigned enable)
+{
+ if (!enable) {
+ /* Disable not supported */
+ return;
+ }
+ switch (pll) {
+ case 2:
+ pll_enable((void *)PLL2_MODE_ADDR);
+ return;
+ case 4:
+ pll_enable((void *)PLL4_MODE_ADDR);
+ return;
+ default:
+ return;
+ };
+}
+
+void acpu_clock_init(void)
+{
+ uint32_t i;
+ uint32_t val;
+ uint32_t size;
+
+ /* Increase VDD level to the final value. */
+ writel((1 << 7) | (VDD_LEVEL << 3), VDD_SVS_PLEVEL_ADDR);
+
+ udelay(1000);
+ const uint32_t *clk_cntl_reg_val = clk_cntl_reg_val_7627A;
+ size = ARRAY_SIZE(clk_cntl_reg_val_7627A);
+ pll_request(2, 1);
+ /* Read clock source select bit. */
+ val = readl(A11S_CLK_SEL_ADDR);
+ i = val & 1;
+
+ /* Jump into table and set every entry. */
+ for (; i < size; i++) {
+
+ val = readl(A11S_CLK_CNTL_ADDR);
+
+ /* Make sure not to disturb already used src */
+ val &= clk_cntl_mask[i%2];
+ val += clk_cntl_reg_val[i];
+ writel(val, A11S_CLK_CNTL_ADDR);
+
+ /* Would need a dmb() here but the whole address space is
+ * strongly ordered, so it should be fine.
+ */
+ val = readl(A11S_CLK_SEL_ADDR);
+ val &= ~(A11S_CLK_SEL_MASK);
+ val |= (A11S_CLK_SEL_MASK & clk_sel_reg_val[i%2]);
+ writel(val, A11S_CLK_SEL_ADDR);
+ udelay(1000);
+ }
+}
+
+#ifdef CONFIG_QC_MMC
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ uint32_t reg = 0;
+ if (mmc_clock_set_rate(sdc_clk[interface], freq) < 0)
+ printf("Failure setting clock rate for MCLK-"
+ "clk_rate : %d\n", freq);
+
+ /* enable clock */
+ if (mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0)
+ printf("Failure enabling MMC Clock!\n");
+
+ reg |= MMC_BOOT_MCI_CLK_ENABLE;
+ reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
+ writel(reg, MMC_BOOT_MCI_CLK);
+}
+
+/* Intialize MMC clock */
+void clock_init_mmc(uint32_t interface)
+{
+ if (mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0)
+ printf("Failure enabling PCLK!\n");
+}
+#endif
+
diff --git a/arch/arm/cpu/armv7/msm7x27a/board.c b/arch/arm/cpu/armv7/msm7x27a/board.c
new file mode 100644
index 0000000..46fc2ea
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7x27a/board.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/sys_proto.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+void set_vector_base(unsigned long addr)
+{
+ __asm__ volatile ("mcr p15, 0, %0, c12, c0, 0" : : "r" (addr));
+}
+
+int dram_init(void)
+{
+ /*TODO: Memory size will change for booting kernel*/
+ gd->ram_size = 0x00100000;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ /* TODO: Memory layout will change for booting kernel
+ * This is intial bring up setup
+ */
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+}
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("Board: %s\n", sysinfo.board_string);
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init()
+{
+ __cpu_early_init();
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/msm7x27a/config.mk b/arch/arm/cpu/armv7/msm7x27a/config.mk
new file mode 100644
index 0000000..f350c2b
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7x27a/config.mk
@@ -0,0 +1,21 @@
+#
+# (C) Copyright 2012
+# Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+#
+#
+
+PLATFORM_CPPFLAGS += -march=armv7-a
diff --git a/arch/arm/cpu/armv7/msm7x27a/gpio.c b/arch/arm/cpu/armv7/msm7x27a/gpio.c
new file mode 100644
index 0000000..f5975e3
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7x27a/gpio.c
@@ -0,0 +1,287 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
+ *
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/proc_comm.h>
+
+#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
+#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
+
+/* output value */
+#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
+#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
+#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
+#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
+#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
+#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 132-107 */
+
+/* same pin map as above, output enable */
+#define GPIO_OE_0 GPIO1_REG(0x10)
+#define GPIO_OE_1 GPIO2_REG(0x08)
+#define GPIO_OE_2 GPIO1_REG(0x14)
+#define GPIO_OE_3 GPIO1_REG(0x18)
+#define GPIO_OE_4 GPIO1_REG(0x1C)
+#define GPIO_OE_5 GPIO1_REG(0x54)
+
+/* same pin map as above, input read */
+#define GPIO_IN_0 GPIO1_REG(0x34)
+#define GPIO_IN_1 GPIO2_REG(0x20)
+#define GPIO_IN_2 GPIO1_REG(0x38)
+#define GPIO_IN_3 GPIO1_REG(0x3C)
+#define GPIO_IN_4 GPIO1_REG(0x40)
+#define GPIO_IN_5 GPIO1_REG(0x44)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define GPIO_INT_EDGE_0 GPIO1_REG(0x60)
+#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
+#define GPIO_INT_EDGE_2 GPIO1_REG(0x64)
+#define GPIO_INT_EDGE_3 GPIO1_REG(0x68)
+#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C)
+#define GPIO_INT_EDGE_5 GPIO1_REG(0xC0)
+
+/* same pin map as above, 1=positive 0=negative */
+#define GPIO_INT_POS_0 GPIO1_REG(0x70)
+#define GPIO_INT_POS_1 GPIO2_REG(0x58)
+#define GPIO_INT_POS_2 GPIO1_REG(0x74)
+#define GPIO_INT_POS_3 GPIO1_REG(0x78)
+#define GPIO_INT_POS_4 GPIO1_REG(0x7C)
+#define GPIO_INT_POS_5 GPIO1_REG(0xBC)
+
+/* same pin map as above, interrupt enable */
+#define GPIO_INT_EN_0 GPIO1_REG(0x80)
+#define GPIO_INT_EN_1 GPIO2_REG(0x60)
+#define GPIO_INT_EN_2 GPIO1_REG(0x84)
+#define GPIO_INT_EN_3 GPIO1_REG(0x88)
+#define GPIO_INT_EN_4 GPIO1_REG(0x8C)
+#define GPIO_INT_EN_5 GPIO1_REG(0xB8)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90)
+#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
+#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94)
+#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98)
+#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C)
+#define GPIO_INT_CLEAR_5 GPIO1_REG(0xB4)
+
+/* same pin map as above, 1=interrupt pending */
+#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0)
+#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
+#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4)
+#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8)
+#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC)
+#define GPIO_INT_STATUS_5 GPIO1_REG(0xB0)
+
+typedef struct gpioregs gpioregs;
+
+struct gpioregs {
+ unsigned out;
+ unsigned in;
+ unsigned int_status;
+ unsigned int_clear;
+ unsigned int_en;
+ unsigned int_edge;
+ unsigned int_pos;
+ unsigned oe;
+};
+
+static gpioregs GPIO_REGS[] = {
+ {
+ .out = GPIO_OUT_0,
+ .in = GPIO_IN_0,
+ .int_status = GPIO_INT_STATUS_0,
+ .int_clear = GPIO_INT_CLEAR_0,
+ .int_en = GPIO_INT_EN_0,
+ .int_edge = GPIO_INT_EDGE_0,
+ .int_pos = GPIO_INT_POS_0,
+ .oe = GPIO_OE_0,
+ },
+ {
+ .out = GPIO_OUT_1,
+ .in = GPIO_IN_1,
+ .int_status = GPIO_INT_STATUS_1,
+ .int_clear = GPIO_INT_CLEAR_1,
+ .int_en = GPIO_INT_EN_1,
+ .int_edge = GPIO_INT_EDGE_1,
+ .int_pos = GPIO_INT_POS_1,
+ .oe = GPIO_OE_1,
+ },
+ {
+ .out = GPIO_OUT_2,
+ .in = GPIO_IN_2,
+ .int_status = GPIO_INT_STATUS_2,
+ .int_clear = GPIO_INT_CLEAR_2,
+ .int_en = GPIO_INT_EN_2,
+ .int_edge = GPIO_INT_EDGE_2,
+ .int_pos = GPIO_INT_POS_2,
+ .oe = GPIO_OE_2,
+ },
+ {
+ .out = GPIO_OUT_3,
+ .in = GPIO_IN_3,
+ .int_status = GPIO_INT_STATUS_3,
+ .int_clear = GPIO_INT_CLEAR_3,
+ .int_en = GPIO_INT_EN_3,
+ .int_edge = GPIO_INT_EDGE_3,
+ .int_pos = GPIO_INT_POS_3,
+ .oe = GPIO_OE_3,
+ },
+ {
+ .out = GPIO_OUT_4,
+ .in = GPIO_IN_4,
+ .int_status = GPIO_INT_STATUS_4,
+ .int_clear = GPIO_INT_CLEAR_4,
+ .int_en = GPIO_INT_EN_4,
+ .int_edge = GPIO_INT_EDGE_4,
+ .int_pos = GPIO_INT_POS_4,
+ .oe = GPIO_OE_4,
+ },
+ {
+ .out = GPIO_OUT_5,
+ .in = GPIO_IN_5,
+ .int_status = GPIO_INT_STATUS_5,
+ .int_clear = GPIO_INT_CLEAR_5,
+ .int_en = GPIO_INT_EN_5,
+ .int_edge = GPIO_INT_EDGE_5,
+ .int_pos = GPIO_INT_POS_5,
+ .oe = GPIO_OE_5,
+ },
+};
+
+static gpioregs *find_gpio(unsigned n, unsigned *bit)
+{
+ if (n > 132)
+ return 0;
+ if (n > 106) {
+ *bit = 1 << (n - 107);
+ return GPIO_REGS + 5;
+ }
+ if (n > 94) {
+ *bit = 1 << (n - 95);
+ return GPIO_REGS + 4;
+ }
+ if (n > 67) {
+ *bit = 1 << (n - 68);
+ return GPIO_REGS + 3;
+ }
+ if (n > 42) {
+ *bit = 1 << (n - 43);
+ return GPIO_REGS + 2;
+ }
+ if (n > 15) {
+ *bit = 1 << (n - 16);
+ return GPIO_REGS + 1;
+ }
+ *bit = 1 << n;
+ return GPIO_REGS + 0;
+}
+
+int gpio_config(unsigned n, unsigned flags)
+{
+ gpioregs *r;
+ unsigned b;
+ unsigned v;
+ r = find_gpio(n, &b);
+ if (!r)
+ return -1;
+
+ v = readl(r->oe);
+ if (flags & GPIO_OUTPUT)
+ writel(v | b, r->oe);
+ else
+ writel(v & (~b), r->oe);
+ return 0;
+}
+
+void gpio_set(unsigned n, unsigned on)
+{
+ gpioregs *r;
+ unsigned b;
+ unsigned v;
+
+ r = find_gpio(n, &b);
+ if (r == 0)
+ return;
+
+ v = readl(r->out);
+ if (on)
+ writel(v | b, r->out);
+ else
+ writel(v & (~b), r->out);
+
+}
+
+int gpio_get(unsigned n)
+{
+ gpioregs *r;
+ unsigned b;
+ r = find_gpio(n, &b);
+ if (r == 0)
+ return 0;
+ return (readl(r->in) & b) ? 1 : 0;
+}
+
+#if 0
+void platform_config_interleaved_mode_gpios(void)
+{
+ /* configure EB2_CS1 through GPIO86 */
+ writel(GPIO_ALT_FUNC_PAGE_REG, 0x56);
+ writel(GPIO_ALT_FUNC_CFG_REG, 0x04);
+ /* configure the EBI2_BUSY1_N through GPIO115 */
+ writel(GPIO_ALT_FUNC_PAGE_REG, 0x73);
+ writel(GPIO_ALT_FUNC_CFG_REG, 0x08);
+}
+
+/* Enables all gpios passed in table*/
+int platform_gpios_enable(const struct msm_gpio *table, int size)
+{
+ int rc;
+ int i;
+ const struct msm_gpio *g;
+ for (i = 0; i < size; i++) {
+ g = table + i;
+ /* Enable gpio */
+ rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE);
+ if (rc)
+ goto err;
+ }
+ return 0;
+err:
+ return rc;
+}
+#endif
+
+
diff --git a/arch/arm/cpu/armv7/msm7x27a/lowlevel_init.S b/arch/arm/cpu/armv7/msm7x27a/lowlevel_init.S
new file mode 100644
index 0000000..e6c4ac1
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7x27a/lowlevel_init.S
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+
+.text
+.code 32
+
+#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
+#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
+
+
+
+
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
+
+.global invalidate_dcache
+invalidate_dcache:
+ mov pc, lr
+
+ .align 5
+.globl lowlevel_init
+lowlevel_init:
+ mov pc, lr @ back to arch calling code
+
+.global reset_cpu
+reset_cpu:
+_loop_forever:
+ b _loop_forever
+
+
+
+.globl __cpu_early_init
+__cpu_early_init:
+
+ //; Zero out r0 for use throughout this code. All other GPRs
+ //; (r1-r3) are set throughout this code to help establish
+ //; a consistent startup state for any code that follows.
+ //; Users should add code at the end of this routine to establish
+ //; their own stack address (r13), add translation page tables, enable
+ //; the caches, etc.
+ push {r5-r12,r14}
+ mov r0, #0x0
+ //; Initialize ASID to zero
+ mcr p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
+
+ //; ICIALL to invalidate entire I-Cache
+ mcr p15, 0, r0, c7, c5, 0 //; ICIALLU
+
+ //; Initialize ADFSR to zero
+ mcr p15, 0, r0, c5, c1, 0 //; ADFSR r0
+
+ //; Ensure the MCR's above have completed their operation before
+ //; continuing
+ DSB
+ ISB
+
+ //;-------------------------------------------------------------------
+ //; There are a number of registers that must be set prior to enabling
+ //; the MMU. The DCAR is one of these registers. We are setting
+ //; it to zero (no access) to easily detect improper setup in subsequent
+ //; code sequences
+ //;-------------------------------------------------------------------
+ //; Setup DACR (Domain Access Control Register) to zero
+ mcr p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
+
+ //;Make sure TLBLKCR is complete before continuing
+ ISB
+
+ //; Invalidate the UTLB
+ mcr p15, 0, r0, c8, c7, 0 //; UTLBIALL
+
+ //; Make sure UTLB request has been presented to macro before continuing
+ ISB
+
+SYSI2:
+ //; Enable Z bit to enable branch prediction (default is off)
+ mrc p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
+ orr r2, r2, #0x00000800
+ mcr p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
+
+ //; Make sure Link stack is initialized with branch and links to
+ //; sequential addresses
+ //; This aids in creating a predictable startup environment
+ bl SEQ1
+SEQ1: bl SEQ2
+SEQ2: bl SEQ3
+SEQ3: bl SEQ4
+SEQ4: bl SEQ5
+SEQ5: bl SEQ6
+SEQ6: bl SEQ7
+SEQ7: bl SEQ8
+SEQ8:
+
+ ISB
+ pop {r5-r12,pc}
+
+
+.ltorg
diff --git a/arch/arm/cpu/armv7/msm7x27a/timer.c b/arch/arm/cpu/armv7/msm7x27a/timer.c
new file mode 100644
index 0000000..0eb4ece
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7x27a/timer.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2 at ti.com>
+ * Syed Moahmmed Khasim <khasim at ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger at sysgo.de>
+ * Alex Zuepke <azu at sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/arch/iomap.h>
+#include <asm/io.h>
+#include <common.h>
+#include <asm/types.h>
+#define TIMER_LOAD_VAL 0x21
+
+#define GPT_ENABLE_CLR_ON_MATCH_EN 2
+#define GPT_ENABLE_EN 1
+#define DGT_ENABLE_CLR_ON_MATCH_EN 2
+#define DGT_ENABLE_EN 1
+
+#define SPSS_TIMER_STATUS_DGT_EN (1 << 0)
+
+
+#define READ_TIMER readl(GPT_COUNT_VAL)
+
+static ulong timestamp;
+static ulong lastinc;
+#define DGT_HZ 6750000 /* Uses LPXO/4 (27.0 MHz / 4) */
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+ writel(0, DGT_ENABLE);
+ return 0;
+}
+/* timer without interrupts */
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+ unsigned int val;
+ usec = (usec * 33 + 1000 - 33) / 1000;
+
+ writel(0, GPT_CLEAR);
+ writel(0, GPT_ENABLE);
+ do {
+ val = 0;
+ val = readl(GPT_COUNT_VAL);
+ } while (val != 0);
+
+ writel(GPT_ENABLE_EN, GPT_ENABLE);
+ do {
+ val = 0;
+ val = readl(GPT_COUNT_VAL);
+ } while (val < usec) ;
+
+ writel(0, GPT_ENABLE);
+ writel(0, GPT_CLEAR);
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER; /* current tick value */
+
+ if (lastinc <= now) { /* normal mode (non roll) */
+ /* normal mode */
+ timestamp += now - lastinc;
+ /* move stamp forward with absolute diff ticks */
+ } else { /* we have overflow of the count down timer */
+ timestamp += now + (TIMER_LOAD_VAL - lastinc);
+ }
+ lastinc = now;
+
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/include/asm/arch-msm7x27a/gpio.h b/arch/arm/include/asm/arch-msm7x27a/gpio.h
new file mode 100644
index 0000000..ca8c4af
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/gpio.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __GPIO_H
+#define __GPIO_H
+
+#ifndef GPIO_INPUT
+#define GPIO_INPUT 0x0000
+#endif
+#ifndef GPIO_OUTPUT
+#define GPIO_OUTPUT 0x0001
+#endif
+
+#define GPIO_LEVEL 0x0000
+#define GPIO_EDGE 0x0010
+
+#define GPIO_RISING 0x0020
+#define GPIO_FALLING 0x0040
+
+#define GPIO_HIGH 0x0020
+#define GPIO_LOW 0x0040
+
+#define GPIO_PULLUP 0x0100
+#define GPIO_PULLDOWN 0x0200
+
+int gpio_config(unsigned nr, unsigned flags);
+void gpio_set(unsigned nr, unsigned on);
+int gpio_get(unsigned nr);
+
+#endif
diff --git a/arch/arm/include/asm/arch-msm7x27a/iomap.h b/arch/arm/include/asm/arch-msm7x27a/iomap.h
new file mode 100644
index 0000000..4c9d434
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/iomap.h
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef _PLATFORM_MSM7627A_IOMAP_H_
+#define _PLATFORM_MSM7627A_IOMAP_H_
+
+#define MSM_GPIO1_BASE 0xA9200000
+#define MSM_GPIO2_BASE 0xA9300000
+
+#define MSM_UART1_BASE 0xA9A00000
+#define MSM_UART2_BASE 0xA9B00000
+#define MSM_UART3_BASE 0xA9C00000
+
+#define MSM_VIC_BASE 0xC0000000
+#define MSM_GPT_BASE 0xC0100000
+
+#define GPT_REG(off) (MSM_GPT_BASE + (off))
+
+#define GPT_MATCH_VAL GPT_REG(0x0000)
+#define GPT_COUNT_VAL GPT_REG(0x0004)
+#define GPT_ENABLE GPT_REG(0x0008)
+#define GPT_CLEAR GPT_REG(0x000C)
+#define DGT_MATCH_VAL GPT_REG(0x0010)
+#define DGT_COUNT_VAL GPT_REG(0x0014)
+#define DGT_ENABLE GPT_REG(0x0018)
+#define DGT_CLEAR GPT_REG(0x001C)
+#define SPSS_TIMER_STATUS GPT_REG(0x0034)
+
+#define MSM_CSR_BASE 0xC0100000
+#define MSM_CLK_CTL_BASE 0xA8600000
+
+#define MSM_SHARED_BASE 0x00100000
+
+#define MSM_SDC1_BASE 0xA0400000
+#define MSM_SDC3_BASE 0xA0600000
+
+#define MIPI_DSI_BASE (0xA1100000)
+#define DSI_PHY_SW_RESET (0xA1100128)
+#define REG_DSI(off) (MIPI_DSI_BASE + (off))
+#define MDP_BASE (0xAA200000)
+#define REG_MDP(off) (MDP_BASE + (off))
+#define DSIPHY_REGULATOR_BASE (0x2CC)
+#define DSIPHY_TIMING_BASE (0x260)
+#define DSIPHY_CTRL_BASE (0x290)
+#define DSIPHY_PLL_BASE (0x200)
+#define DSIPHY_STRENGTH_BASE (0x2A0)
+
+/* Range 0 - 4 */
+#define DSIPHY_REGULATOR_CTRL(x) REG_DSI(DSIPHY_REGULATOR_BASE + (x) * 4)
+/* Range 0 - 11 */
+#define DSIPHY_TIMING_CTRL(x) REG_DSI(DSIPHY_TIMING_BASE + (x) * 4)
+/* Range 0 - 3 */
+#define DSIPHY_CTRL(x) REG_DSI(DSIPHY_CTRL_BASE + (x) * 4)
+/* Range 0 - 2 */
+#define DSIPHY_STRENGTH_CTRL(x) REG_DSI(DSIPHY_STRENGTH_BASE + (x) * 4)
+/* Range 0 - 19 */
+#define DSIPHY_PLL_CTRL(x) REG_DSI(DSIPHY_PLL_BASE + (x) * 4)
+
+#define MDP_DMA_P_CONFIG (0xAA290000)
+#define MDP_DMA_P_OUT_XY (0xAA290010)
+#define MDP_DMA_P_SIZE (0xAA290004)
+#define MDP_DMA_P_BUF_ADDR (0xAA290008)
+#define MDP_DMA_P_BUF_Y_STRIDE (0xAA29000C)
+
+#define MDP_DSI_VIDEO_EN (0xAA2F0000)
+#define MDP_DSI_VIDEO_HSYNC_CTL (0xAA2F0004)
+#define MDP_DSI_VIDEO_VSYNC_PERIOD (0xAA2F0008)
+#define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH (0xAA2F000C)
+#define MDP_DSI_VIDEO_DISPLAY_HCTL (0xAA2F0010)
+#define MDP_DSI_VIDEO_DISPLAY_V_START (0xAA2F0014)
+#define MDP_DSI_VIDEO_DISPLAY_V_END (0xAA2F0018)
+#define MDP_DSI_VIDEO_BORDER_CLR (0xAA2F0028)
+#define MDP_DSI_VIDEO_HSYNC_SKEW (0xAA2F0030)
+#define MDP_DSI_VIDEO_CTL_POLARITY (0xAA2F0038)
+#define MDP_DSI_VIDEO_TEST_CTL (0xAA2F0034)
+
+#define MDP_DMA_P_START REG_MDP(0x0000C)
+#define MDP_DMA_S_START REG_MDP(0x00010)
+#define MDP_DISP_INTF_SEL REG_MDP(0x00038)
+#define MDP_MAX_RD_PENDING_CMD_CONFIG REG_MDP(0x0004C)
+#define MDP_INTR_ENABLE REG_MDP(0x00020)
+#define MDP_INTR_CLEAR REG_MDP(0x00028)
+#define MDP_DSI_CMD_MODE_ID_MAP REG_MDP(0x000A0)
+#define MDP_DSI_CMD_MODE_TRIGGER_EN REG_MDP(0x000A4)
+
+#define MDP_TEST_MODE_CLK REG_MDP(0xF0000)
+#define MDP_INTR_STATUS REG_MDP(0x00054)
+#endif
diff --git a/arch/arm/include/asm/arch-msm7x27a/mmc.h b/arch/arm/include/asm/arch-msm7x27a/mmc.h
new file mode 100644
index 0000000..15a8cd4
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/mmc.h
@@ -0,0 +1,399 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MMC_H__
+#define __MMC_H__
+
+#ifndef MMC_SLOT
+#define MMC_SLOT 0
+#endif
+
+#include <common.h>
+#include <part.h>
+#include <mmc.h>
+
+/*
+ * Define Macros for SDCC Registers
+ */
+/* 8 bit */
+#define MMC_BOOT_MCI_POWER 0x000
+
+/* MCICMD output control - 6th bit */
+#ifdef PLATFORM_MSM7X30
+#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
+#define MMC_BOOT_MCI_PWR_OFF 0x00
+#define MMC_BOOT_MCI_PWR_UP 0x01
+#define MMC_BOOT_MCI_PWR_ON 0x01
+#else
+#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
+#define MMC_BOOT_MCI_PWR_OFF 0x00
+#define MMC_BOOT_MCI_PWR_UP 0x02
+#define MMC_BOOT_MCI_PWR_ON 0x03
+#endif
+
+/* 16 bits */
+#define MMC_BOOT_MCI_CLK 0x004
+/* Enable MCI bus clock - 0: clock disabled 1: enabled */
+#define MMC_BOOT_MCI_CLK_ENABLE (1 << 8)
+/* Disable clk o/p when bus idle- 0:always enabled 1:enabled when bus active */
+#define MMC_BOOT_MCI_CLK_PWRSAVE (1 << 9)
+/* Enable Widebus mode - 00: 1 bit mode 10:4 bit mode 01/11: 8 bit mode */
+#define MMC_BOOT_MCI_CLK_WIDEBUS_MODE (3 << 10)
+#define MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT 0
+#define MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT (2 << 10)
+#define MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT (1 << 10)
+/* Enable flow control- 0: disable 1: enable */
+#define MMC_BOOT_MCI_CLK_ENA_FLOW (1 << 12)
+/* Set/clear to select rising/falling edge for data/cmd output */
+#define MMC_BOOT_MCI_CLK_INVERT_OUT (1 << 13)
+/* Select to lach data/cmd coming in falling/rising/feedbk/loopbk of MCIclk */
+#define MMC_BOOT_MCI_CLK_IN_FALLING 0x0
+#define MMC_BOOT_MCI_CLK_IN_RISING (1 << 14)
+#define MMC_BOOT_MCI_CLK_IN_FEEDBACK (2 << 14)
+#define MMC_BOOT_MCI_CLK_IN_LOOPBACK (3 << 14)
+
+/* Bus Width */
+#define MMC_BOOT_BUS_WIDTH_1_BIT 0
+#define MMC_BOOT_BUS_WIDTH_4_BIT 2
+#define MMC_BOOT_BUS_WIDTH_8_BIT 3
+
+/* 32 bits */
+#define MMC_BOOT_MCI_ARGUMENT 0x008
+
+/* 16 bits */
+#define MMC_BOOT_MCI_CMD 0x00C
+/* Command Index: 0 -5 */
+/* Waits for response if set */
+#define MMC_BOOT_MCI_CMD_RESPONSE (1 << 6)
+/* Receives a 136-bit long response if set */
+#define MMC_BOOT_MCI_CMD_LONGRSP (1 << 7)
+/* If set, CPSM disables command timer and waits for interrupt */
+#define MMC_BOOT_MCI_CMD_INTERRUPT (1 << 8)
+/* If set waits for CmdPend before starting to send a command */
+#define MMC_BOOT_MCI_CMD_PENDING (1 << 9)
+/* CPSM is enabled if set */
+#define MMC_BOOT_MCI_CMD_ENABLE (1 << 10)
+/* If set PROG_DONE status bit asserted when busy is de-asserted */
+#define MMC_BOOT_MCI_CMD_PROG_ENA (1 << 11)
+/* To indicate that this is a Command with Data (for SDIO interrupts) */
+#define MMC_BOOT_MCI_CMD_DAT_CMD (1 << 12)
+/* Signals the next command to be an abort (stop) command. Always read 0 */
+#define MMC_BOOT_MCI_CMD_MCIABORT (1 << 13)
+/* Waits for Command Completion Signal if set */
+#define MMC_BOOT_MCI_CMD_CCS_ENABLE (1 << 14)
+/* If set sends CCS disable sequence */
+#define MMC_BOOT_MCI_CMD_CCS_DISABLE (1 << 15)
+
+#define MMC_BOOT_MCI_RESP_CMD 0x010
+
+#define MMC_BOOT_MCI_RESP_0 0x014
+#define MMC_BOOT_MCI_RESP_1 0x018
+#define MMC_BOOT_MCI_RESP_2 0x01C
+#define MMC_BOOT_MCI_RESP_3 0x020
+
+#define MMC_BOOT_MCI_DATA_TIMER 0x024
+#define MMC_BOOT_MCI_DATA_LENGTH 0x028
+/* 16 bits */
+#define MMC_BOOT_MCI_DATA_CTL 0x02C
+/* Data transfer enabled */
+#define MMC_BOOT_MCI_DATA_ENABLE (1 << 0)
+/* Data transfer direction - 0: controller to card 1:card to controller */
+#define MMC_BOOT_MCI_DATA_DIR (1 << 1)
+/* Data transfer mode - 0: block data transfer 1: stream data transfer */
+#define MMC_BOOT_MCI_DATA_MODE (1 << 2)
+/* Enable DM interface - 0: DM disabled 1: DM enabled */
+#define MMC_BOOT_MCI_DATA_DM_ENABLE (1 << 3)
+/* Data block length in bytes (1-4096) */
+#define MMC_BOOT_MCI_BLKSIZE_POS 4
+#define MMC_BOOT_MCI_DATA_COUNT 0x030
+#define MMC_BOOT_MCI_STATUS 0x034
+/* Command response received - CRC check failed */
+#define MMC_BOOT_MCI_STAT_CMD_CRC_FAIL (1 << 0)
+/* Data block sent/received - CRC check failed */
+#define MMC_BOOT_MCI_STAT_DATA_CRC_FAIL (1 << 1)
+/* Command resonse timeout */
+#define MMC_BOOT_MCI_STAT_CMD_TIMEOUT (1 << 2)
+/* Data timeout */
+#define MMC_BOOT_MCI_STAT_DATA_TIMEOUT (1 << 3)
+/* Transmit FIFO underrun error */
+#define MMC_BOOT_MCI_STAT_TX_UNDRUN (1 << 4)
+/* Receive FIFO overrun error */
+#define MMC_BOOT_MCI_STAT_RX_OVRRUN (1 << 5)
+/* Command response received - CRC check passed */
+#define MMC_BOOT_MCI_STAT_CMD_RESP_END (1 << 6)
+/* Command sent - no response required */
+#define MMC_BOOT_MCI_STAT_CMD_SENT (1 << 7)
+/* Data end - data counter zero */
+#define MMC_BOOT_MCI_STAT_DATA_END (1 << 8)
+/* Start bit not detected on all data signals in wide bus mode */
+#define MMC_BOOT_MCI_STAT_START_BIT_ERR (1 << 9)
+/* Data block sent/received - CRC check passed */
+#define MMC_BOOT_MCI_STAT_DATA_BLK_END (1 << 10)
+/* Command transfer in progress */
+#define MMC_BOOT_MCI_STAT_CMD_ACTIVE (1 << 11)
+/* Data transmit in progress */
+#define MMC_BOOT_MCI_STAT_TX_ACTIVE (1 << 12)
+/* Data receive in progress */
+#define MMC_BOOT_MCI_STAT_RX_ACTIVE (1 << 13)
+/* Transmit FIFO half full */
+#define MMC_BOOT_MCI_STAT_TX_FIFO_HFULL (1 << 14)
+/* Receive FIFO half full */
+#define MMC_BOOT_MCI_STAT_RX_FIFO_HFULL (1 << 15)
+/* Transmit FIFO full */
+#define MMC_BOOT_MCI_STAT_TX_FIFO_FULL (1 << 16)
+/* Receive FIFO full */
+#define MMC_BOOT_MCI_STAT_RX_FIFO_FULL (1 << 17)
+/* Transmit FIFO empty */
+#define MMC_BOOT_MCI_STAT_TX_FIFO_EMPTY (1 << 18)
+/* Receive FIFO empty */
+#define MMC_BOOT_MCI_STAT_RX_FIFO_EMPTY (1 << 19)
+/* Data available in transmit FIFO */
+#define MMC_BOOT_MCI_STAT_TX_DATA_AVLBL (1 << 20)
+/* Data available in receive FIFO */
+#define MMC_BOOT_MCI_STAT_RX_DATA_AVLBL (1 << 21)
+/* SDIO interrupt indicator for wake-up */
+#define MMC_BOOT_MCI_STAT_SDIO_INTR (1 << 22)
+/* Programming done */
+#define MMC_BOOT_MCI_STAT_PROG_DONE (1 << 23)
+/* CE-ATA command completion signal detected */
+#define MMC_BOOT_MCI_STAT_ATA_CMD_CMPL (1 << 24)
+/* SDIO interrupt indicator for normal operation */
+#define MMC_BOOT_MCI_STAT_SDIO_INTR_OP (1 << 25)
+/* Commpand completion signal timeout */
+#define MMC_BOOT_MCI_STAT_CCS_TIMEOUT (1 << 26)
+
+#define MMC_BOOT_MCI_STATIC_STATUS (MMC_BOOT_MCI_STAT_CMD_CRC_FAIL| \
+ MMC_BOOT_MCI_STAT_DATA_CRC_FAIL| \
+ MMC_BOOT_MCI_STAT_CMD_TIMEOUT| \
+ MMC_BOOT_MCI_STAT_DATA_TIMEOUT| \
+ MMC_BOOT_MCI_STAT_TX_UNDRUN| \
+ MMC_BOOT_MCI_STAT_RX_OVRRUN| \
+ MMC_BOOT_MCI_STAT_CMD_RESP_END| \
+ MMC_BOOT_MCI_STAT_CMD_SENT| \
+ MMC_BOOT_MCI_STAT_DATA_END| \
+ MMC_BOOT_MCI_STAT_START_BIT_ERR| \
+ MMC_BOOT_MCI_STAT_DATA_BLK_END| \
+ MMC_BOOT_MCI_SDIO_INTR_CLR| \
+ MMC_BOOT_MCI_STAT_PROG_DONE| \
+ MMC_BOOT_MCI_STAT_ATA_CMD_CMPL |\
+ MMC_BOOT_MCI_STAT_CCS_TIMEOUT)
+
+#define MMC_BOOT_MCI_CLEAR 0x038
+#define MMC_BOOT_MCI_CMD_CRC_FAIL_CLR (1 << 0)
+#define MMC_BOOT_MCI_DATA_CRC_FAIL_CLR (1 << 1)
+#define MMC_BOOT_MCI_CMD_TIMEOUT_CLR (1 << 2)
+#define MMC_BOOT_MCI_DATA_TIMEOUT_CLR (1 << 3)
+#define MMC_BOOT_MCI_TX_UNDERRUN_CLR (1 << 4)
+#define MMC_BOOT_MCI_RX_OVERRUN_CLR (1 << 5)
+#define MMC_BOOT_MCI_CMD_RESP_END_CLR (1 << 6)
+#define MMC_BOOT_MCI_CMD_SENT_CLR (1 << 7)
+#define MMC_BOOT_MCI_DATA_END_CLR (1 << 8)
+#define MMC_BOOT_MCI_START_BIT_ERR_CLR (1 << 9)
+#define MMC_BOOT_MCI_DATA_BLK_END_CLR (1 << 10)
+#define MMC_BOOT_MCI_SDIO_INTR_CLR (1 << 22)
+#define MMC_BOOT_MCI_PROG_DONE_CLR (1 << 23)
+#define MMC_BOOT_MCI_ATA_CMD_COMPLR_CLR (1 << 24)
+#define MMC_BOOT_MCI_CCS_TIMEOUT_CLR (1 << 25)
+
+#define MMC_BOOT_MCI_INT_MASK0 0x03C
+#define MMC_BOOT_MCI_CMD_CRC_FAIL_MASK (1 << 0)
+#define MMC_BOOT_MCI_DATA_CRC_FAIL_MASK (1 << 1)
+#define MMC_BOOT_MCI_CMD_TIMEOUT_MASK (1 << 2)
+#define MMC_BOOT_MCI_DATA_TIMEOUT_MASK (1 << 3)
+#define MMC_BOOT_MCI_TX_OVERRUN_MASK (1 << 4)
+#define MMC_BOOT_MCI_RX_OVERRUN_MASK (1 << 5)
+#define MMC_BOOT_MCI_CMD_RESP_END_MASK (1 << 6)
+#define MMC_BOOT_MCI_CMD_SENT_MASK (1 << 7)
+#define MMC_BOOT_MCI_DATA_END_MASK (1 << 8)
+#define MMC_BOOT_MCI_START_BIT_ERR_MASK (1 << 9)
+#define MMC_BOOT_MCI_DATA_BLK_END_MASK (1 << 10)
+#define MMC_BOOT_MCI_CMD_ACTIVE_MASK (1 << 11)
+#define MMC_BOOT_MCI_TX_ACTIVE_MASK (1 << 12)
+#define MMC_BOOT_MCI_RX_ACTIVE_MASK (1 << 13)
+#define MMC_BOOT_MCI_TX_FIFO_HFULL_MASK (1 << 14)
+#define MMC_BOOT_MCI_RX_FIFO_HFULL_MASK (1 << 15)
+#define MMC_BOOT_MCI_TX_FIFO_FULL_MASK (1 << 16)
+#define MMC_BOOT_MCI_RX_FIFO_FULL_MASK (1 << 17)
+#define MMC_BOOT_MCI_TX_FIFO_EMPTY_MASK (1 << 18)
+#define MMC_BOOT_MCI_RX_FIFO_EMPTY_MASK (1 << 19)
+#define MMC_BOOT_MCI_TX_DATA_AVLBL_MASK (1 << 20)
+#define MMC_BOOT_MCI_RX_DATA_AVLBL_MASK (1 << 21)
+#define MMC_BOOT_MCI_SDIO_INT_MASK (1 << 22)
+#define MMC_BOOT_MCI_PROG_DONE_MASK (1 << 23)
+#define MMC_BOOT_MCI_ATA_CMD_COMPL_MASK (1 << 24)
+#define MMC_BOOT_MCI_SDIO_INT_OPER_MASK (1 << 25)
+#define MMC_BOOT_MCI_CCS_TIME_OUT_MASK (1 << 26)
+
+#define MMC_BOOT_MCI_INT_MASK1 0x040
+
+#define MMC_BOOT_MCI_FIFO_COUNT 0x044
+
+#define MMC_BOOT_MCI_CCS_TIMER 0x0058
+
+#define MMC_BOOT_MCI_FIFO 0x080
+
+/* OCR Register */
+#define MMC_BOOT_OCR_17_19 (1 << 7)
+#define MMC_BOOT_OCR_27_36 (0x1FF << 15)
+#define MMC_BOOT_OCR_SEC_MODE (2 << 29)
+#define MMC_BOOT_OCR_BUSY (1 << 31)
+
+/* Commands type */
+#define MMC_BOOT_CMD_BCAST (1 << 0)
+#define MMC_BOOT_CMD_BCAST_W_RESP (1 << 1)
+#define MMC_BOOT_CMD_ADDRESS (1 << 2)
+#define MMC_BOOT_CMD_ADDR_DATA_XFER (1 << 3)
+
+/* Card Status bits (R1 register) */
+#define MMC_BOOT_R1_AKE_SEQ_ERROR (1 << 3)
+#define MMC_BOOT_R1_APP_CMD (1 << 5)
+#define MMC_BOOT_R1_RDY_FOR_DATA (1 << 6)
+#define MMC_BOOT_R1_CURR_STATE_IDLE (0 << 9)
+#define MMC_BOOT_R1_CURR_STATE_RDY (1 << 9)
+#define MMC_BOOT_R1_CURR_STATE_IDENT (2 << 9)
+#define MMC_BOOT_R1_CURR_STATE_STBY (3 << 9)
+#define MMC_BOOT_R1_CURR_STATE_TRAN (4 << 9)
+#define MMC_BOOT_R1_CURR_STATE_DATA (5 << 9)
+#define MMC_BOOT_R1_CURR_STATE_RCV (6 << 9)
+#define MMC_BOOT_R1_CURR_STATE_PRG (7 << 9)
+#define MMC_BOOT_R1_CURR_STATE_DIS (8 << 9)
+#define MMC_BOOT_R1_ERASE_RESET (1 << 13)
+#define MMC_BOOT_R1_CARD_ECC_DISABLED (1 << 14)
+#define MMC_BOOT_R1_WP_ERASE_SKIP (1 << 15)
+#define MMC_BOOT_R1_ERROR (1 << 19)
+#define MMC_BOOT_R1_CC_ERROR (1 << 20)
+#define MMC_BOOT_R1_CARD_ECC_FAILED (1 << 21)
+#define MMC_BOOT_R1_ILLEGAL_CMD (1 << 22)
+#define MMC_BOOT_R1_COM_CRC_ERR (1 << 23)
+#define MMC_BOOT_R1_LOCK_UNLOCK_FAIL (1 << 24)
+#define MMC_BOOT_R1_CARD_IS_LOCKED (1 << 25)
+#define MMC_BOOT_R1_WP_VIOLATION (1 << 26)
+#define MMC_BOOT_R1_ERASE_PARAM (1 << 27)
+#define MMC_BOOT_R1_ERASE_SEQ_ERR (1 << 28)
+#define MMC_BOOT_R1_BLOCK_LEN_ERR (1 << 29)
+#define MMC_BOOT_R1_ADDR_ERR (1 << 30)
+#define MMC_BOOT_R1_OUT_OF_RANGE (1 << 31)
+
+/* Macros for Common Errors */
+#define MMC_BOOT_E_SUCCESS 0
+#define MMC_BOOT_E_FAILURE 1
+/* Not used..use instead TIMEOUT in include/mmc.h */
+#define MMC_BOOT_E_TIMEOUT 2
+#define MMC_BOOT_E_INVAL 3
+#define MMC_BOOT_E_CRC_FAIL 4
+#define MMC_BOOT_E_INIT_FAIL 5
+#define MMC_BOOT_E_CMD_INDX_MISMATCH 6
+#define MMC_BOOT_E_RESP_VERIFY_FAIL 7
+#define MMC_BOOT_E_NOT_SUPPORTED 8
+#define MMC_BOOT_E_CARD_BUSY 9
+#define MMC_BOOT_E_MEM_ALLOC_FAIL 10
+#define MMC_BOOT_E_CLK_ENABLE_FAIL 11
+#define MMC_BOOT_E_CMMC_DECODE_FAIL 12
+#define MMC_BOOT_E_CID_DECODE_FAIL 13
+#define MMC_BOOT_E_BLOCKLEN_ERR 14
+#define MMC_BOOT_E_ADDRESS_ERR 15
+#define MMC_BOOT_E_DATA_CRC_FAIL 16
+#define MMC_BOOT_E_DATA_TIMEOUT 17
+#define MMC_BOOT_E_RX_OVRRUN 18
+#define MMC_BOOT_E_VREG_SET_FAILED 19
+#define MMC_BOOT_E_GPIO_CFG_FAIL 20
+#define MMC_BOOT_E_DATA_ADM_ERR 21
+
+/* EXT_CSD */
+#define MMC_BOOT_ACCESS_WRITE 0x3
+#define MMC_BOOT_EXT_CMMC_HS_TIMING 185
+#define MMC_BOOT_EXT_CMMC_BUS_WIDTH 183
+
+#define MMC_BOOT_EXT_USER_WP 171
+#define MMC_BOOT_EXT_ERASE_GROUP_DEF 175
+#define MMC_BOOT_EXT_HC_WP_GRP_SIZE 221
+#define MMC_BOOT_EXT_HC_ERASE_GRP_SIZE 224
+
+#define MMC_BOOT_US_PERM_WP_EN 2
+#define MMC_BOOT_US_PWR_WP_DIS 3
+
+#define MMC_BOOT_US_PERM_WP_DIS (1<<4)
+#define MMC_BOOT_US_PWR_WP_EN 1
+
+/* For SD */
+#define MMC_BOOT_SD_HC_VOLT_SUPPLIED 0x000001AA
+#define MMC_BOOT_SD_NEG_OCR 0x00FF8000
+#define MMC_BOOT_SD_HC_HCS 0x40000000
+#define MMC_BOOT_SD_DEV_READY 0x80000000
+#define MMC_BOOT_SD_SWITCH_HS 0x80FFFFF1
+
+/* Data structure definitions */
+
+#define MMC_BOOT_XFER_MODE_BLOCK 0
+#define MMC_BOOT_XFER_MODE_STREAM 1
+#define MMC_BOOT_PROGRAM_ENABLED 2
+
+
+#define MMC_RCA 2
+
+#define MMC_BOOT_MAX_COMMAND_RETRY 1000
+#define MMC_BOOT_RD_BLOCK_LEN 512
+#define MMC_BOOT_WR_BLOCK_LEN 512
+
+/* We have 16 32-bits FIFO registers */
+#define MMC_BOOT_MCI_FIFO_DEPTH 16
+#define MMC_BOOT_MCI_HFIFO_COUNT (MMC_BOOT_MCI_FIFO_DEPTH / 2)
+#define MMC_BOOT_MCI_FIFO_SIZE (MMC_BOOT_MCI_FIFO_DEPTH * 4)
+
+#define MAX_PARTITIONS 64
+
+#define MMC_BOOT_CHECK_PATTERN 0xAA /* 10101010b */
+
+#define MMC_CLK_400KHZ 400000
+#define MMC_CLK_144KHZ 144000
+#define MMC_CLK_20MHZ 20000000
+#define MMC_CLK_24MHZ 24000000
+#define MMC_CLK_25MHZ 25000000
+#define MMC_CLK_26MHZ 26000000
+#define MMC_CLK_48MHZ 48000000
+#define MMC_CLK_50MHZ 49152000
+#define MMC_CLK_52MHZ 52000000
+
+#define MMC_CLK_ENABLE 1
+#define MMC_CLK_DISABLE 0
+
+#if 0
+#define MSM_SDC1_BASE 0x12400000
+#define MSM_SDC2_BASE 0x12140000
+#define MSM_SDC3_BASE 0x12180000
+#define MSM_SDC4_BASE 0x121C0000
+#endif
+struct mmc_priv {
+ unsigned int instance;
+ unsigned int base;
+ unsigned int rd_timeout_ns; /* for read timeout */
+};
+
+void mmc_boot_set_ios(struct mmc *mmc);
+int mmc_boot_send_command_map(struct mmc *mmc,
+ struct mmc_cmd *cmd,
+ struct mmc_data *data);
+unsigned long int mmc_boot_mci_reg(unsigned long base, unsigned long offset);
+unsigned int mmc_boot_main(struct mmc *mmc);
+
+extern void clock_config_mmc(uint32_t interface, uint32_t freq);
+extern void clock_init_mmc(uint32_t interface);
+#endif
+
diff --git a/arch/arm/include/asm/arch-msm7x27a/proc_comm.h b/arch/arm/include/asm/arch-msm7x27a/proc_comm.h
new file mode 100644
index 0000000..e919794
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/proc_comm.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __PROC_COMM_H_
+#define __PROC_COMM_H_
+
+void usb_clock_init(void);
+void lcdc_clock_init(unsigned rate);
+void mdp_clock_init(unsigned rate);
+void uart3_clock_init(void);
+void uart2_clock_init(void);
+void uart1_clock_init(void);
+void mddi_clock_init(unsigned num, unsigned rate);
+void reboot(unsigned reboot_reason);
+int mmc_clock_enable_disable(unsigned id, unsigned enable);
+int mmc_clock_set_rate(unsigned id, unsigned rate);
+int mmc_clock_get_rate(unsigned id);
+int gpio_tlmm_config(unsigned config, unsigned disable);
+int vreg_set_level(unsigned id, unsigned mv);
+int vreg_enable(unsigned id);
+int vreg_disable(unsigned id);
+
+#endif
+
+
diff --git a/arch/arm/include/asm/arch-msm7x27a/sys_proto.h b/arch/arm/include/asm/arch-msm7x27a/sys_proto.h
new file mode 100644
index 0000000..d5d5125
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/sys_proto.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+void pll8_enable(void);
+void clock_init(void);
+void __cpu_early_init(void);
+#endif
+
--
1.7.1
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