[U-Boot] [PATCH 05/10] mx5 clocks: Fix get_periph_clk()

[Benoît Thébaudeau]

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau at advansee.com>
Cc: Stefano Babic <sbabic at denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   42 ++++++++++----------
 1 file changed, 22 insertions(+), 20 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index 408fb54..b92ac49 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -281,6 +281,26 @@ static u32 get_fpm(void)
 #endif
 
 /*
+ * This function returns the low power audio clock.
+ */
+static u32 get_lp_apm(void)
+{
+	u32 ret_val = 0;
+	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+
+	if (ccsr & MXC_CCM_CCSR_LP_APM)
+#if defined(CONFIG_MX51)
+		ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
+#endif
+	else
+		ret_val = CONFIG_SYS_MX5_HCLK;
+
+	return ret_val;
+}
+
+/*
  * Get mcu main rate
  */
 u32 get_mcu_main_clk(void)
@@ -310,6 +330,8 @@ u32 get_periph_clk(void)
 		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
 	case 1:
 		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+	case 2:
+		return get_lp_apm();
 	default:
 		return 0;
 	}
@@ -392,26 +414,6 @@ static u32 get_uart_clk(void)
 }
 
 /*
- * This function returns the low power audio clock.
- */
-static u32 get_lp_apm(void)
-{
-	u32 ret_val = 0;
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
-
-	if (ccsr & MXC_CCM_CCSR_LP_APM)
-#if defined(CONFIG_MX51)
-		ret_val = get_fpm();
-#elif defined(CONFIG_MX53)
-		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
-#endif
-	else
-		ret_val = CONFIG_SYS_MX5_HCLK;
-
-	return ret_val;
-}
-
-/*
  * get cspi clock rate.
  */
 static u32 imx_get_cspiclk(void)