[U-Boot] [PATCH 5/6] mx35: Add default pin initializers
Benoît Thébaudeau
benoit.thebaudeau at advansee.com
Tue Aug 14 21:40:13 CEST 2012
Create default pin initialization functions for the default iomux function
assignments of the main peripherals.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau at advansee.com>
Cc: Stefano Babic <sbabic at denx.de>
---
.../arch/arm/cpu/arm1136/mx35/generic.c | 206 ++++++++++++++++++++
.../arch/arm/include/asm/arch-mx35/sys_proto.h | 8 +
2 files changed, 214 insertions(+)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c
index 986b1f9..37187ad 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c
+++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c
@@ -28,6 +28,8 @@
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <netdev.h>
@@ -389,7 +391,211 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return -1;
}
+#ifdef CONFIG_MXC_UART
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+void mx35_uart1_init_pins(void)
+{
+ int in_pad, out_pad;
+
+ /* Set up pins for UART1. */
+ mxc_request_iomux(MX35_PIN_RXD1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_TXD1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_RTS1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_CTS1, MUX_CONFIG_FUNC);
+
+ in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_RXD1, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_TXD1, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_RTS1, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_CTS1, out_pad);
+}
+#endif
+#endif
+
+#ifdef CONFIG_I2C_MXC
+#if CONFIG_SYS_I2C_BASE == I2C1_BASE_ADDR
+void mx35_i2c1_init_pins(void)
+{
+ int io_pad;
+
+ /* Set up pins for I2C1. */
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ io_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, io_pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, io_pad);
+}
+#endif
+
+#if CONFIG_SYS_I2C_BASE == I2C2_BASE_ADDR
+void mx35_i2c2_init_pins(void)
+{
+ int io_pad;
+
+ /* Set up pins for I2C2. */
+ mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ io_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, io_pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, io_pad);
+}
+#endif
+
+u32 imx_get_i2cclk(void)
+{
+ return mxc_get_clock(MXC_IPG_PERCLK);
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+void mx35_cspi1_init_pins(void)
+{
+ int act_lo_pad, act_hi_pad;
+
+ /* Set up pins for CSPI1. */
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_FUNC);
+
+ act_lo_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ act_hi_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PD |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_CSPI1_SCLK, act_hi_pad);
+ mxc_iomux_set_pad(MX35_PIN_CSPI1_SPI_RDY, act_lo_pad);
+ mxc_iomux_set_pad(MX35_PIN_CSPI1_MOSI, act_hi_pad);
+ mxc_iomux_set_pad(MX35_PIN_CSPI1_MISO, act_hi_pad);
+ mxc_iomux_set_pad(MX35_PIN_CSPI1_SS0, act_lo_pad);
+ mxc_iomux_set_pad(MX35_PIN_CSPI1_SS1, act_lo_pad);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MXC
+#if CONFIG_MXC_USB_PORT == 0
+void mx35_usbotg_init_pins(void)
+{
+ int in_pad, out_pad;
+
+ /* Set up pins for USBOTG. */
+ mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+#endif
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC1_BASE_ADDR
+void mx35_esdhc1_init_pins(void)
+{
+ int out_pad, io_pad;
+
+ /* Set up pins for eSDHC1. */
+ mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_47K_PU | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
+ io_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_47K_PU | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
+
+ mxc_iomux_set_pad(MX35_PIN_SD1_CMD, io_pad);
+ mxc_iomux_set_pad(MX35_PIN_SD1_CLK, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, io_pad);
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA1, io_pad);
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA2, io_pad);
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, io_pad);
+}
+#endif
+#endif
+
#ifdef CONFIG_FEC_MXC
+void mx35_fec_init_pins(void)
+{
+ int in_pad, out_pad, io_pad;
+
+ /* Set up pins for FEC. */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+ in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ io_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_22K_PU | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_COL, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_MDC, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, io_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_CRS, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, in_pad);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, out_pad);
+}
+
/*
* The MX35 has no fuse for MAC, return a NULL MAC
*/
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/sys_proto.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/sys_proto.h
index 9c0d513..3c46106 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/sys_proto.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/sys_proto.h
@@ -27,4 +27,12 @@
u32 get_cpu_rev(void);
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+void mx35_uart1_init_pins(void);
+void mx35_i2c1_init_pins(void);
+void mx35_i2c2_init_pins(void);
+void mx35_cspi1_init_pins(void);
+void mx35_usbotg_init_pins(void);
+void mx35_esdhc1_init_pins(void);
+void mx35_fec_init_pins(void);
+
#endif
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