[U-Boot] [PATCH 2/4] efikamx: remove drive strength hack from early_init_f and move it to the DCD
Matt Sealey
matt at genesi-usa.com
Fri Aug 17 20:19:20 CEST 2012
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets
executed. Rather than setting up DDR, putting U-Boot in place, and getting
into pre-relocation init to set up DDR again, just do it once in the correct
place. This also solves an issue where the Smarttop DDR pad settings were
being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still
got room in the DCD to do so.
Signed-off-by: Matt Sealey <matt at genesi-usa.com>
---
board/genesi/mx51_efikamx/efikamx.c | 77 -------------------------
board/genesi/mx51_efikamx/imximage_mx.cfg | 89 +++++++++++++----------------
2 files changed, 40 insertions(+), 126 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index e88b2ed..12371c9 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -597,85 +597,8 @@ void efikamx_toggle_led(uint32_t mask)
/*
* Board initialization
*/
-static void init_drive_strength(void)
-{
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
-
- /* Setting pad options */
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-}
-
int board_early_init_f(void)
{
- init_drive_strength();
-
setup_iomux_uart();
setup_iomux_spi();
setup_iomux_led();
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
index 6fe0ff9..ac9aa9a 100644
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -1,7 +1,7 @@
#
+# Copyright (C) 2009 Pegatron Corporation
# Copyright (C) 2010 Marek Vasut <marek.vasut at gmail.com>
-#
-# BASED ON: imx51evk
+# Copyright (C) 2009-2012 Genesi USA, Inc.
#
# (C) Copyright 2009
# Stefano Babic DENX Software Engineering sbabic at denx.de.
@@ -43,48 +43,44 @@ BOOT_FROM spi
# Address absolute address of the register
# value value to be stored in the register
-# Setting IOMUXC
-DATA 4 0x73fa88a0 0x000
-DATA 4 0x73fa850c 0x20c5
-DATA 4 0x73fa8510 0x20c5
-DATA 4 0x73fa883c 0x5
-DATA 4 0x73fa8848 0x5
-DATA 4 0x73fa84b8 0xe7
-DATA 4 0x73fa84bc 0x45
-DATA 4 0x73fa84c0 0x45
-DATA 4 0x73fa84c4 0x45
-DATA 4 0x73fa84c8 0x45
-DATA 4 0x73fa8820 0x0
-DATA 4 0x73fa84a4 0x5
-DATA 4 0x73fa84a8 0x5
-DATA 4 0x73fa84ac 0xe5
-DATA 4 0x73fa84b0 0xe5
-DATA 4 0x73fa84b4 0xe5
-DATA 4 0x73fa84cc 0xe5
-DATA 4 0x73fa84d0 0xe4
+# Essential GPIO settings to be done as early as possible
+# PCBID pad settings are all the defaults except #2 which needs HVE off
+DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
+DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
+DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
+DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE
+DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
+DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
+DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-DATA 4 0x73fa882c 0x4
-DATA 4 0x73fa88a4 0x4
-DATA 4 0x73fa88ac 0x4
-DATA 4 0x73fa88b8 0x4
+# DDR bus IOMUX PAD settings
+DATA 4 0x73fa850c 0x20c5 # SDODT1
+DATA 4 0x73fa8510 0x20c5 # SDODT0
+DATA 4 0x73fa84ac 0xc5 # SDWE
+DATA 4 0x73fa84b0 0xc5 # SDCKE0
+DATA 4 0x73fa84b4 0xc5 # SDCKE1
+DATA 4 0x73fa84cc 0xc5 # DRAM_CS0
+DATA 4 0x73fa84d0 0xc5 # DRAM_CS1
+DATA 4 0x73fa882c 0x2 # DRAM_B4
+DATA 4 0x73fa88a4 0x2 # DRAM_B0
+DATA 4 0x73fa88ac 0x2 # DRAM_B1
+DATA 4 0x73fa88b8 0x2 # DRAM_B2
+DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0
+DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
+DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
+DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
-DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
-DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
-DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
-DATA 4 0x83fd9004 0x3f3574aa
-# ESDCTL_ESDCFG1
-DATA 4 0x83fd900c 0x3f3574aa
+# Setting DDR for Micron
+# 13 Rows, 10 Cols, 32 bit
+# SREF=4 Micron Model CAS=3 BL=4
+DATA 4 0x83fd9000 0x82a20000 # ESDCTL_ESDCTL0
+DATA 4 0x83fd9008 0x82a20000 # ESDCTL_ESDCTL1
+DATA 4 0x83fd9010 0xcaaaf6d0 # ESDCTL_ESDMISC
+DATA 4 0x83fd9004 0x3f3574aa # ESDCTL_ESDCFG0
+DATA 4 0x83fd900c 0x3f3574aa # ESDCTL_ESDCFG1
# Init DRAM on CS0
-# ESDCTL_ESDSCR
-DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x04008008 # ESDCTL_ESDSCR
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
DATA 4 0x83fd9014 0x00448019
@@ -110,13 +106,8 @@ DATA 4 0x83fd9014 0x0632801c
DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0040801d
DATA 4 0x83fd9014 0x00008004
-
-# Write to CTL0
-DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
-DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
-DATA 4 0x83fd9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
-DATA 4 0x83fd9034 0x90000000
+DATA 4 0x83fd9000 0xb2a20000 # Write to CTL0
+DATA 4 0x83fd9008 0xb2a20000 # Write to CTL1
+DATA 4 0x83fd9010 0x000ad6d0 # ESDMISC
+DATA 4 0x83fd9034 0x90000000 # ESDCTL_ESDCDLYGD
DATA 4 0x83fd9014 0x00000000
--
1.7.9.5
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