[U-Boot] [PATCH 03/11] powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2

[York Sun]

Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun at freescale.com>
---
 arch/powerpc/cpu/mpc85xx/speed.c      |    5 +++--
 arch/powerpc/include/asm/immap_85xx.h |    7 +++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 203f53d..6bf49ee 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao at motorola.com)
@@ -85,7 +85,8 @@ void get_sys_info (sys_info_t * sysInfo)
 	sysInfo->freqDDRBus = sysclk;
 
 	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
+			 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 	if (mem_pll_rat > 2)
 		sysInfo->freqDDRBus *= mem_pll_rat;
 	else
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 2a27be9..ed42918 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1755,6 +1755,13 @@ typedef struct ccsr_gur {
 	u32	brrl;		/* Boot release */
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
+#ifndef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
+#else
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#endif
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
-- 
1.7.0.4