[U-Boot] [PATCHv2 1/2] mpc85xx: Initial SP alignment is wrong.

[Andy Fleming]

On Mon, Jul 23, 2012 at 3:58 PM, Joakim Tjernlund
<Joakim.Tjernlund at transmode.se> wrote:
> PowerPC mandates SP to be 16 bytes aligned.
> Furthermore, a stack frame is added, pointing to the reset vector
> which may in the way when gdb is walking the stack because
> the reset vector may not accessible depending on emulator settings.
> Also use a temp register so gdb doesn't pick up intermediate values.
>
> Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund at transmode.se>
> ---
>
>  v2 - Address Scott Wood's comments
>  arch/powerpc/cpu/mpc85xx/start.S |   16 +++++-----------
>  1 files changed, 5 insertions(+), 11 deletions(-)
>
> diff --git arch/powerpc/cpu/mpc85xx/start.S arch/powerpc/cpu/mpc85xx/start.S


Why are your patches different from everyone else's? When I try to
apply this, I get errors because it can't find
"powerpc/cpu/mpc85xx...". git am leaves off the first directory,
because the usual practice is to send patches with these filenames:

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S

I fixed it by hand, but let's not make that a habit. Is there some
setting that I don't have that would make it so I could ignore this?


> index 8d66cf1..4973682 100644
> --- arch/powerpc/cpu/mpc85xx/start.S
> +++ arch/powerpc/cpu/mpc85xx/start.S
> @@ -848,18 +848,12 @@ version_string:
>         .globl  _start_cont
>  _start_cont:
>         /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
> -       lis     r1,CONFIG_SYS_INIT_RAM_ADDR at h
> -       ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET at l
> -
> +       lis     r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
> +       ori     r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
>         li      r0,0
> -       stwu    r0,-4(r1)
> -       stwu    r0,-4(r1)               /* Terminate call chain */
> -
> -       stwu    r1,-8(r1)               /* Save back chain and move SP */
> -       lis     r0,RESET_VECTOR at h       /* Address of reset vector */
> -       ori     r0,r0,RESET_VECTOR at l
> -       stwu    r1,-8(r1)               /* Save back chain and move SP */
> -       stw     r0,+12(r1)              /* Save return addr (underflow vect) */
> +       stw     r0,0(r3)        /* Terminate Back Chain */
> +       stw     r0,+4(r3)       /* NULL return address. */
> +       mr      r1,r3           /* Transfer to SP(r1) */
>
>         GET_GOT
>         bl      cpu_init_early_f
> --
> 1.7.3.4
>
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