[U-Boot] [PATCH 03/16] Blackfin: Bf60x: support big cplb page

[Mike Frysinger]

On Monday 20 August 2012 04:00:21 Bob Liu wrote:
> On Wed, Aug 8, 2012 at 12:48 PM, Mike Frysinger wrote:
> > On Tuesday 07 August 2012 04:07:42 Bob Liu wrote:
> >> --- a/arch/blackfin/lib/board.c
> >> +++ b/arch/blackfin/lib/board.c
> >> 
> >>  void init_cplbtables(void)
> >>  {
> >> ...
> >> +#if defined(__ADSPBF60x__)
> >> +     icplb_add(0x0, 0x0);
> > 
> > err, why ?
> 
> Because other place use value "i" for both icplb and dcplb this make
> them consistent.

why not add an ICPLB entry for the same region you just added a DCPLB entry 
for ?  we can directly execute out of the flash memory region ...

> >> +     cplb_page_size = (4 * 1024 * 1024);
> >> +     cplb_page_mask = (~(cplb_page_size - 1));
> > 
> > why only use CPLBs of 4 megs for external memory on BF60x ?  you would
> > want to maximize the usage of 16MiB to reduce CPLB overhead.
> 
> Bf60x will reinit cplb_page_size/mask behind.

sorry, i don't understand what you mean
-mike
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