[U-Boot] [PATCH v2] efikamx: sync Smartbook DDR settings in DCD with those found in Genesi's production U-Boot

[Matt Sealey]

We have no idea where the DCD was derived from for Smartbook support, but they
differ from the Smarttop settings, MX51EVK settings and certainly don't
correspond to any shipped or development version of U-Boot that Genesi has ever
had on any Smartbook.

So, copy the calibrated, verified settings from the U-Boot as shipped with every
Smartbook since retail production. Remove those few settings that just set the
POR defaults which have already been confirmed for the previous Smarttop DCD
change.

One of the lines is specific to i.MX51 TO3 designs and therefore TO2 Smartbooks
will possibly not work so reliably with this new DCD; that said, TO2 Smartbooks
basically don't exist at retail and the number of units in the world is less
than 5 (3 of which are at the Genesi office or owned by Genesi employees).

Many hours of memory testing confirms the new settings are stable.

Patch v2:
 * picked the correct commit from our development tree, correcting tuned DDR ODF setting
   (which was correct anyway)

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
Cc: Stefano Babic <sbabic at denx.de>
Cc: Marek Vasut <marex at denx.de>
---
 board/genesi/mx51_efikamx/imximage_sb.cfg |   44 +++++++++++++----------------
 1 file changed, 19 insertions(+), 25 deletions(-)

diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
index 878146f..26d259f 100644
--- a/board/genesi/mx51_efikamx/imximage_sb.cfg
+++ b/board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -1,5 +1,7 @@
 #
+# Copyright (C) 2009 Pegatron Corporation
 # Copyright (C) 2010 Marek Vasut <marek.vasut at gmail.com>
+# Copyright (C) 2009-2012 Genesi USA, Inc.
 #
 # BASED ON: imx51evk
 #
@@ -43,30 +45,22 @@ BOOT_FROM	spi
 #	Address	  absolute address of the register
 #	value	  value to be stored in the register
 
-# Setting IOMUXC
-DATA 4 0x73fa88a0 0x200
-DATA 4 0x73fa850c 0x20c3
-DATA 4 0x73fa8510 0x20c3
-DATA 4 0x73fa883c 0x2
-DATA 4 0x73fa8848 0x2
-DATA 4 0x73fa84b8 0xe7
-DATA 4 0x73fa84bc 0x45
-DATA 4 0x73fa84c0 0x45
-DATA 4 0x73fa84c4 0x45
-DATA 4 0x73fa84c8 0x45
-DATA 4 0x73fa8820 0x0
-DATA 4 0x73fa84a4 0x5
-DATA 4 0x73fa84a8 0x5
-DATA 4 0x73fa84ac 0xe3
-DATA 4 0x73fa84b0 0xe3
-DATA 4 0x73fa84b4 0xe3
-DATA 4 0x73fa84cc 0xe3
-DATA 4 0x73fa84d0 0xe2
-
-DATA 4 0x73fa882c 0x4
-DATA 4 0x73fa88a4 0x4
-DATA 4 0x73fa88ac 0x4
-DATA 4 0x73fa88b8 0x4
+# DDR bus IOMUX PAD settings
+DATA 4 0x73fa88a0 0x200		# GRP_INMODE1
+DATA 4 0x73fa850c 0x20c5	# SDODT1
+DATA 4 0x73fa8510 0x20c5	# SDODT0
+DATA 4 0x73fa8848 0x4		# DDR_A1
+DATA 4 0x73fa84b8 0xe7		# DRAM_SDCLK
+DATA 4 0x73fa84bc 0x45		# DRAM_SDQS0
+DATA 4 0x73fa84c0 0x45		# DRAM_SDQS1
+DATA 4 0x73fa84c4 0x45		# DRAM_SDQS2
+DATA 4 0x73fa84c8 0x45		# DRAM_SDQS3
+DATA 4 0x73fa8820 0x0		# DDRPKS
+DATA 4 0x73fa84ac 0xe5		# SDWE
+DATA 4 0x73fa84b0 0xe5		# SDCKE0
+DATA 4 0x73fa84b4 0xe5		# SDCKE1
+DATA 4 0x73fa84cc 0xe5		# DRAM_CS0
+DATA 4 0x73fa84d0 0xe4		# DRAM_CS1
 
 # Setting DDR for micron
 # 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
@@ -108,7 +102,7 @@ DATA 4 0x83fd9014 0x00008014
 DATA 4 0x83fd9014 0x00008014
 DATA 4 0x83fd9014 0x0632801c
 DATA 4 0x83fd9014 0x0380801d
-DATA 4 0x83fd9014 0x0040801d
+DATA 4 0x83fd9014 0x0042801d
 DATA 4 0x83fd9014 0x00008004
 
 # Write to CTL0
-- 
1.7.9.5