[U-Boot] [PATCH] ARM926: Add mb to the cache invalidate/flush

[Marek Vasut]

Add memory barrier to cache invalidate and flush calls. This prevents
compiler from reordering the code around these, possibly generating
invalid results.

Signed-off-by: Marek Vasut <marex at denx.de>
CC: Albert Aribaud <albert.u.boot at aribaud.net>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Otavio Salvador <otavio at ossystems.com.br>
Cc: Stefano Babic <sbabic at denx.de>
---
 arch/arm/cpu/arm926ejs/cache.c |    8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 2740ad7..c4102f6 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -67,7 +67,8 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
 		return;
 
 	while (start < stop) {
-		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+		asm volatile("mcr p15, 0, %0, c7, c6, 1\n"
+				: : "r"(start) : "memory");
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 }
@@ -78,11 +79,12 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 		return;
 
 	while (start < stop) {
-		asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
+		asm volatile("mcr p15, 0, %0, c7, c14, 1\n"
+				: : "r"(start) : "memory");
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 
-	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0) : "memory");
 }
 
 void flush_cache(unsigned long start, unsigned long size)
-- 
1.7.10.4