[U-Boot] [PATCH] MX28: SPI: Fix CTRL0 not being written at end of DMA transfer

[Marek Vasut]

The final DMA descriptor doesn't properly write CTRL0 register
during the DMA transfer. Properly write CTRL0 to make sure the
transmission is complete.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Otavio Salvador <otavio at ossystems.com.br>
Cc: Stefano Babic <sbabic at denx.de>
---
 drivers/spi/mxs_spi.c |   20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 168dbe4..5ee0ea1 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -226,6 +226,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 	uint32_t cache_data_count;
 	int dmach;
 	int tl;
+	int ret = 0;
 
 	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 
@@ -302,12 +303,25 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 			MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 	if (flags & SPI_XFER_END) {
 		ctrl0 &= ~SSP_CTRL0_LOCK_CS;
-		dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC;
+		ctrl0 |= SSP_CTRL0_IGNORE_CRC;
+		dp->cmd.pio_words[0] = ctrl0;
 	}
 	mxs_dma_desc_append(dmach, dp);
 
 	if (mxs_dma_go(dmach))
-		return -EINVAL;
+		ret = -EINVAL;
+
+	/*
+	 * The DMA contains further hidden gems, like the last transfer
+	 * not writing the CTRL0 PIO word properly. Write the PIO word
+	 * directly here for proper operation. This issue was detected
+	 * on S25FL064P chip by issuing:
+	 *
+	 *   sf probe 2:0 ; sf read 0x42000000 0 0x800000 ; sf probe 2:0
+	 *
+	 * This resulted in garbled subsequent probe.
+	 */
+	writel(ctrl0, &ssp_regs->hw_ssp_ctrl0_reg);
 
 	/* The data arrived into DRAM, invalidate cache over them */
 	if (!write) {
@@ -315,7 +329,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 			(uint32_t)(data + cache_data_count));
 	}
 
-	return 0;
+	return ret;
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-- 
1.7.10.4