[U-Boot] [PATCH v2 7/7] Tegra30: Add/enable Cardhu build (T30 reference board)

Simon Glass sjg at chromium.org
Mon Dec 10 20:04:43 CET 2012


Hi Tom,

On Mon, Dec 10, 2012 at 9:05 AM, Tom Warren <twarren.nvidia at gmail.com> wrote:
> Simon,
>
> On Sat, Dec 8, 2012 at 1:00 PM, Simon Glass <sjg at chromium.org> wrote:
>> Hi,
>>
>> On Tue, Dec 4, 2012 at 2:41 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>>> On 12/04/2012 01:40 PM, Lucas Stach wrote:
>>>> Hi Tom,
>>>>
>>>> Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren:
>>>> [...]
>>>>>
>>>>>>
>>>>>>> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
>>>>>>
>>>>>> I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
>>>>>> up that way.
>>>>>
>>>>> See my previous reply. In the internal U-Boot repo I ported from, PLLP
>>>>> was initially set to 216MHz, then sped up to 408MHz. When this first
>>>>> round of patches is in, I can address going to 408MHz first thing.
>>>>>
>>>> Is running the PLL_P at 408MHz something which requires a lot of work?
>>>> If not, please do this and fold it into this patchset. It doesn't look
>>>> too nice adding things to upstream which have to be changed/removed
>>>> immediately after going in.
>>>
>>> Naively I'd have to agree here; it seems that programming the PLL for
>>> the correct rate would probably "just work" right from the outset? After
>>> all, if the code runs OK with the higher rate enabled a little later in
>>> boot, I see no reason it shouldn't run OK with that exact same rate the
>>> whole way through.
>>
>> From memory, the problem was originally that we wanted to be able to
>> configure the PLL speed at run time, because we we using both speeds.
>> Since T30 now apparently only uses 408MHz, it should be ok to set it
>> once and hard-code it.
>>
>> Regards,
>> Simon
>>
> Thanks. As I remember it, it was a user-config option for early T30
> boards to run at 216MHz or 408MHz. The 408MHz PLLP change generated a
> lot of email traffic on what the best output clocks (pllp_out1 thru 4)
> would be for the various periphs, subclocks, etc.
>
> When I did the original bringup for upstream U-Boot on my (older)
> Cardhu, I wanted to start at 216MHz first, then step up to 408MHz when
> I was at a stable point. Much like when I rebuilt my Mustang - I took
> it out around the block first, to be sure everything was working OK
> before I took it on the highway ;)
>
> I'm running OK at 408MHz on my Cardhu T33. I'll resubmit V3 of the
> patchset in the next day or so.

Sounds good, thanks. It would be good to get this in.

Regards,
Simon

>
> Thanks,
>
> Tom
>>>
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