[U-Boot] Possible Denx m28evk ethernet problem + solution

[Marek Vasut]

> Hi Marek,
> 
> I'm currently working on U-Boot support for the Freescale i.mx28evk board.

This is already supported mainline.

> It started out as an update of the old Freescale supplied U-Boot 2009.08,
> but it ended up in reconfiguring your work on the Denx m28evk module.
> Today I stumbled upon a problem with Ethernet.
> 
> It turned out that communication with the PHYs didn't work, because the SoC
> isn't supplying ENET_CLK.

The DENX board is actually ok, working properly, you don't understand what's 
going on in there. The RMII mode of PHY supplies clock to CPU. Read the manual 
before you start doing some wild acusations please :-)

> The Ethernet clock is configured properly by
> cpu_eth_init in ./arch/arm/cpu/arm926ejs/mx28/mx28.c. But later in the
> boot process, board_eth_init in board/denx/m28evk/m28evk.c tries to
> configure the Ethernet clock again. Unfortunately that second
> configuration is just disabling the clock:
> 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
> 		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
> 		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
> After removing this line, I measured a 25MHz clock, communication with the
> PHYs worked and I successfully tftp'ed a kernel from my server.

It's different -- M28EVK and MX28EVK are.
> 
> Does Ethernet on your board work?

Yes.

> Does you board have an external clock
> oscillator for the PHYs?

Yes.

> If not, do you agree with removing this line?

No.

> 
> Cheers,
> 
>         Robert.

M