[U-Boot] [PATCH v2 3/9] openrisc: Add cpu files

[Mike Frysinger]

On Friday 06 January 2012 08:22:54 Stefan Kristiansson wrote:
> On Thu, Jan 05, 2012 at 06:15:48PM -0500, Mike Frysinger wrote:
> > On Thursday 22 December 2011 06:39:32 Stefan Kristiansson wrote:
> > > On Thu, Dec 22, 2011 at 10:09:30AM +0100, Michal Simek wrote:
> > > > Stefan Kristiansson wrote:
> > > > >+
> > > > >+void dcache_enable(void)
> > > > >+{
> > > > >+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
> > > > >+	asm volatile("l.nop");
> > > > >+	asm volatile("l.nop");
> > > > >+	asm volatile("l.nop");
> > > > >+	asm volatile("l.nop");
> > > > >+	asm volatile("l.nop");
> > > > >+	asm volatile("l.nop");
> > > > >+	asm volatile("l.nop");
> > > > >+	asm volatile("l.nop");
> > > > 
> > > > This is interesting. Are there 8 nops?
> > > > Is there any reason for that? Is it just any waiting?
> > > > If yes, maybe it will be worth to add any comment.
> > > 
> > > Yes, the number of nops are kind of arbitrary,
> > > they are there to add some headroom for the cache
> > > to startup without any load/stores in flight.
> > > 
> > > But you are right, a comment about this might be in place.
> > 
> > this is usually why the ISA provides some sort of sync or latch
> > mechanism. that way code is deterministic instead of being unsettling
> > arbitrary (like it is here).
> 
> The OpenRISC ISA does provide synch mechanisms, but they are unfortunately
> optional and not supported by the (currently) only open implementation
> (or1200).

sounds like a CONFIG knob for people :).  i imagine the # of nop's require 
depends heavily on how the core is laid out in hardware, the speed, etc...
-mike
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