[U-Boot] [PATCH] tegra: mmc: Support operation with dcache enabled

[Mike Frysinger]

On Wednesday 21 December 2011 16:10:16 Stephen Warren wrote:
> Simon Glass wrote at Wednesday, December 21, 2011 1:03 PM:
> > When the data cache is enabled we must flush on write and invalidate
> > on read. We also check that buffers are aligned to data cache lines
> > boundaries. With recent work in U-Boot this should generally be the case
> > but the warnings will catch problems.
> 
> Conceptually this seems fine, but shouldn't the MMC driver core be doing
> the cache management, so all platforms without cache coherency can
> benefit from it?

if the driver bitbangs things out (like SPI/MMC), then the core doing it would 
be a waste wouldn't it ?

a better question might be how does Linux handle it ?  does it force the 
drivers to do it, or does the core take care of things ?
-mike
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