[U-Boot] [PATCH V2] ARMV7: Add support for TRATS board
HeungJun, Kim
riverful.kim at samsung.com
Mon Jan 9 07:05:32 CET 2012
Hi Minkyu Kang,
Any other structures is existed in the arch/arm/include/asm/arch-exynos/*.
So, I'm fitting the codes at this. But,
> -----Original Message-----
> From: Minkyu Kang [mailto:promsoft at gmail.com]
> Sent: Monday, January 09, 2012 11:42 AM
> To: HeungJun, Kim
> Cc: u-boot at lists.denx.de; kyungmin.park at samsung.com; mk7.kang at samsung.com
> Subject: Re: [U-Boot] [PATCH V2] ARMV7: Add support for TRATS board
>
> Dear HeungJun, Kim,
>
> On 6 January 2012 21:55, HeungJun, Kim <riverful.kim at samsung.com> wrote:
> > This patch adds support for Samsung TRATS board
> >
> > Signed-off-by: HeungJun, Kim <riverful.kim at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> > MAINTAINERS | 4 +
> > board/samsung/trats/Makefile | 45 ++
> > board/samsung/trats/lowlevel_init.S | 50 +++
> > board/samsung/trats/lowlevel_util.c | 137 ++++++
> > board/samsung/trats/trats.c | 250 +++++++++++
> > board/samsung/trats/trats_setup.h | 812
> +++++++++++++++++++++++++++++++++++
> > boards.cfg | 1 +
> > include/configs/trats.h | 216 ++++++++++
> > 8 files changed, 1515 insertions(+), 0 deletions(-)
> > create mode 100644 board/samsung/trats/Makefile
> > create mode 100644 board/samsung/trats/lowlevel_init.S
> > create mode 100644 board/samsung/trats/lowlevel_util.c
> > create mode 100644 board/samsung/trats/trats.c
> > create mode 100644 board/samsung/trats/trats_setup.h
> > create mode 100644 include/configs/trats.h
> >
> > diff --git a/board/samsung/trats/lowlevel_init.S
> b/board/samsung/trats/lowlevel_init.S
> > new file mode 100644
> > index 0000000..9159063
> > --- /dev/null
> > +++ b/board/samsung/trats/lowlevel_init.S
> > @@ -0,0 +1,50 @@
> > +/*
> > + * Lowlevel setup for TRATS board based on EXYNOS4210
> > + *
> > + * Copyright (C) 2011 Samsung Electronics
> > + * Heungjun Kim <riverful.kim at samsung.com>
> > + * Kyungmin Park <kyungmin.park at samsung.com>
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <config.h>
> > +#include <version.h>
> > +#include <asm/arch/cpu.h>
> > +#include <asm/arch/clock.h>
> > +#include "trats_setup.h"
> > +
> > + .globl pmu_init
> > + .globl uart_init
> > + .globl watchdog_disable
> > + .globl clock_init
> > + .globl pmic_reset
> > +
> > + .globl lowlevel_init
> > +lowlevel_init:
> > + push {lr}
> > +
> > + bl pmic_reset @ PMIC reset
> > + bl clock_init @ Init Clock
> > + bl watchdog_disable @ Disable Watchdog
> > + bl uart_init @ Init UART
> > + bl pmu_init @ Init PMU
> > +
> > + pop {pc}
> > + nop
> > diff --git a/board/samsung/trats/lowlevel_util.c
> b/board/samsung/trats/lowlevel_util.c
> > new file mode 100644
> > index 0000000..d67a095
> > --- /dev/null
> > +++ b/board/samsung/trats/lowlevel_util.c
> > @@ -0,0 +1,137 @@
> > +/*
> > + * Copyright (C) 2011 Samsung Electronics
> > + * Heungjun Kim <riverful.kim at samsung.com>
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include "trats_setup.h"
> > +
> > +void pmic_reset(void)
> > +{
> > + u32 base = EXYNOS4_GPIO_PART2_BASE;
> > + u32 gpio;
> > +
> > + gpio = readl(base + EXYNOS4_GPIO_X2_CON_OFFSET);
> > + gpio &= ~EXYNOS4_GPIO_X2_CON_MASK;
> > + gpio |= EXYNOS4_GPIO_X2_CON_VAL;
> > + writel(EXYNOS4_GPIO_X2_CON_VAL, base + EXYNOS4_GPIO_X2_CON_OFFSET);
> > +
> > + gpio = readl(base + EXYNOS4_GPIO_X2_DAT_OFFSET);
> > + gpio |= EXYNOS4_GPIO_X2_DAT_VAL;
> > + writel(gpio, base + EXYNOS4_GPIO_X2_DAT_OFFSET);
> > +}
>
> Please use structures instead of defines.
>
> > +
> > +void clock_init(void)
> > +{
> > + u32 base = EXYNOS4_CLOCK_BASE;
> > +
> > + writel(CLK_SRC_CPU_VAL, base + CLK_SRC_CPU_OFFSET);
> > + writel(CLK_DIV_CPU0_VAL, base + CLK_DIV_CPU0_OFFSET);
> > + writel(CLK_DIV_CPU1_VAL, base + CLK_DIV_CPU1_OFFSET);
> > + writel(CLK_DIV_DMC0_VAL, base + CLK_DIV_DMC0_OFFSET);
> > + writel(CLK_DIV_DMC1_VAL, base + CLK_DIV_DMC1_OFFSET);
> > +
> > + writel(CLK_SRC_TOP0_VAL, base + CLK_SRC_TOP0_OFFSET);
> > + writel(CLK_SRC_FSYS_VAL, base + CLK_SRC_FSYS_OFFSET);
> > + writel(CLK_SRC_PERIL0_VAL, base + CLK_SRC_PERIL0_OFFSET);
> > +
> > + writel(CLK_DIV_LEFTBUS_VAL, base + CLK_DIV_LEFTBUS_OFFSET);
> > + writel(CLK_DIV_RIGHTBUS_VAL, base + CLK_DIV_RIGHTBUS_OFFSET);
> > + writel(CLK_DIV_TOP_VAL, base + CLK_DIV_TOP_OFFSET);
> > + writel(CLK_DIV_FSYS1_VAL, base + CLK_DIV_FSYS1_OFFSET);
> > + writel(CLK_DIV_FSYS2_VAL, base + CLK_DIV_FSYS2_OFFSET);
> > + writel(CLK_DIV_FSYS3_VAL, base + CLK_DIV_FSYS3_OFFSET);
> > + writel(CLK_DIV_PERIL0_VAL, base + CLK_DIV_PERIL0_OFFSET);
> > +
> > + /* PLL Setting */
> > + writel(PLL_LOCKTIME, base + APLL_LOCK_OFFSET);
> > + writel(PLL_LOCKTIME, base + MPLL_LOCK_OFFSET);
> > + writel(PLL_LOCKTIME, base + EPLL_LOCK_OFFSET);
> > + writel(PLL_LOCKTIME, base + VPLL_LOCK_OFFSET);
> > + writel(APLL_CON1_VAL, base + APLL_CON1_OFFSET);
> > + writel(APLL_CON0_VAL, base + APLL_CON0_OFFSET);
> > + writel(MPLL_CON1_VAL, base + MPLL_CON1_OFFSET);
> > + writel(MPLL_CON0_VAL, base + MPLL_CON0_OFFSET);
> > + writel(EPLL_CON1_VAL, base + EPLL_CON1_OFFSET);
> > + writel(EPLL_CON0_VAL, base + EPLL_CON0_OFFSET);
> > + writel(VPLL_CON1_VAL, base + VPLL_CON1_OFFSET);
> > + writel(VPLL_CON0_VAL, base + VPLL_CON0_OFFSET);
> > +
> > + /* Clock Gating */
> > + writel(CLK_GATE_IP_CAM_VAL, base + CLK_GATE_IP_CAM_OFFSET);
> > + writel(CLK_GATE_IP_VP_VAL, base + CLK_GATE_IP_VP_OFFSET);
> > + writel(CLK_GATE_IP_MFC_VAL, base + CLK_GATE_IP_MFC_OFFSET);
> > + writel(CLK_GATE_IP_G3D_VAL, base + CLK_GATE_IP_G3D_OFFSET);
> > + writel(CLK_GATE_IP_IMAGE_VAL, base + CLK_GATE_IP_IMAGE_OFFSET);
> > + writel(CLK_GATE_IP_LCD0_VAL, base + CLK_GATE_IP_LCD0_OFFSET);
> > + writel(CLK_GATE_IP_LCD1_VAL, base + CLK_GATE_IP_LCD1_OFFSET);
> > + writel(CLK_GATE_IP_FSYS_VAL, base + CLK_GATE_IP_FSYS_OFFSET);
> > + writel(CLK_GATE_IP_GPS_VAL, base + CLK_GATE_IP_GPS_OFFSET);
> > + writel(CLK_GATE_IP_PERIL_VAL, base + CLK_GATE_IP_PERIL_OFFSET);
> > + writel(CLK_GATE_IP_PERIR_VAL, base + CLK_GATE_IP_PERIR_OFFSET);
> > + writel(CLK_GATE_BLOCK_VAL, base + CLK_GATE_BLOCK_OFFSET);
> > +}
>
> ditto.
>
> > +
> > +void watchdog_disable(void)
> > +{
> > + u32 base = EXYNOS4_WATCHDOG_BASE;
> > + writel(0, base);
> > +}
> > +
> > +void uart_init(void)
> > +{
> > + u32 base = EXYNOS4_GPIO_PART1_BASE;
> > +
> > + writel(EXYNOS4_GPIO_A0_CON_VAL, base + EXYNOS4_GPIO_A0_CON_OFFSET);
> > + writel(EXYNOS4_GPIO_A1_CON_VAL, base + EXYNOS4_GPIO_A1_CON_OFFSET);
> > +
> > + /* UART_SEL */
> > + base = EXYNOS4_GPIO_PART2_BASE;
> > + writel(EXYNOS4_GPIO_Y4_CON_VAL, base + EXYNOS4_GPIO_Y4_CON_OFFSET);
> > + writel(EXYNOS4_GPIO_Y4_PUD_VAL, base + EXYNOS4_GPIO_Y4_PUD_OFFSET);
> > + writel(EXYNOS4_GPIO_Y4_DAT_VAL, base + EXYNOS4_GPIO_Y4_DAT_OFFSET);
>
> ditto.
>
> > +
> > + base = EXYNOS4_UART_BASE;
> > + base += EXYNOS4_DEFAULT_UART_OFFSET;
> > + writel(ULCON_VAL, base + ULCON_OFFSET);
> > + writel(UCON_VAL, base + UCON_OFFSET);
> > + writel(UFCON_VAL, base + UFCON_OFFSET);
> > + writel(UBRDIV_VAL, base + UBRDIV_OFFSET);
> > + writel(UFRACVAL_VAL, base + UFRACVAL_OFFSET);
>
> Actually, we don't need this.
> It's duplicated setting.
> Please remove it.
>
> > +}
> > +
> > +void pmu_init(void)
> > +{
> > + u32 base = EXYNOS4_POWER_BASE;
> > +
> > + /* PS HOLD */
> > + base += EXYNOS4_PS_HOLD_CON_OFFSET;
> > + writel(EXYNOS4_PS_HOLD_CON_VAL, base);
> > +
> > + /* Set power down */
> > + base += POWER_DOWN_OFFSET;
> > + writel(0, base + POWER_TV_CONFIGURATION_OFFSET);
> > + writel(0, base + POWER_MFC_CONFIGURATION_OFFSET);
> > + writel(0, base + POWER_G3D_CONFIGURATION_OFFSET);
> > + writel(0, base + POWER_LCD_CONFIGURATION_OFFSET);
> > + writel(0, base + POWER_GPS_CONFIGURATION_OFFSET);
>
> Please use structures instead of defines.
I found there is only the definition EXYNOS4_POWER_BASE, not a structure
about the power in the arch/arm/include/asm/arch-exynos/*.
So, I think it's good to put pmu_init() as this for now, and
to change after including the definitions and structures about the power.
How about your thought?
Thanks and Regards,
Heungjun Kim
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