[U-Boot] [PATCH v2 3/4] EXYNOS: Add SMDK5250 board support
Chander Kashyap
chander.kashyap at linaro.org
Mon Jan 9 07:40:14 CET 2012
SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
Signed-off-by: Chander Kashyap <chander.kashyap at linaro.org>
---
Changes for v2:
- This patch is bifurcated into borad support and SoC support
- Fixed typo: s/EEYNOS/EXYNOS
- Squashed patch "SMDK5250: enable device tree support" in this.
MAINTAINERS | 1 +
board/samsung/smdk5250/Makefile | 48 +++
board/samsung/smdk5250/lowlevel_init.S | 528 +++++++++++++++++++++++++++
board/samsung/smdk5250/mem_setup.S | 600 +++++++++++++++++++++++++++++++
board/samsung/smdk5250/smdk5250.c | 125 +++++++
board/samsung/smdk5250/smdk5250_setup.h | 589 ++++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/smdk5250.h | 185 ++++++++++
8 files changed, 2077 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/Makefile
create mode 100644 board/samsung/smdk5250/lowlevel_init.S
create mode 100644 board/samsung/smdk5250/mem_setup.S
create mode 100644 board/samsung/smdk5250/smdk5250.c
create mode 100644 board/samsung/smdk5250/smdk5250_setup.h
create mode 100644 include/configs/smdk5250.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4bf12b5..f62b03e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -705,6 +705,7 @@ Chander Kashyap <k.chander at samsung.com>
origen ARM ARMV7 (EXYNOS4210 SoC)
SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
+ SMDK5250 ARM ARMV7 (EXYNOS5250 SoC)
Torsten Koschorrek <koschorrek at synertronixx.de>
scb9328 ARM920T (i.MXL)
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
new file mode 100644
index 0000000..a26f896
--- /dev/null
+++ b/board/samsung/smdk5250/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+SOBJS := lowlevel_init.o
+SOBJS += mem_setup.o
+COBJS += smdk5250.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL := $(obj).depend $(LIB)
+
+all: $(ALL)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S
new file mode 100644
index 0000000..ecf1d69
--- /dev/null
+++ b/board/samsung/smdk5250/lowlevel_init.S
@@ -0,0 +1,528 @@
+/*
+ * Lowlevel setup for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include "smdk5250_setup.h"
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ */
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE
+
+ .globl lowlevel_init
+lowlevel_init:
+
+ /* use iROM stack in bl2 */
+ ldr sp, =0x02050000
+
+ push {lr}
+
+ /* r5 has always zero */
+ mov r5, #0
+ ldr r7, =EXYNOS5_GPIO_PART1_BASE
+
+ /* check reset status */
+ ldr r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
+ ldr r1, [r0]
+
+ /* AFTR wakeup reset */
+ ldr r2, =S5P_CHECK_DIDLE
+ cmp r1, r2
+ beq exit_wakeup
+
+ /* LPA wakeup reset */
+ ldr r2, =S5P_CHECK_LPA
+ cmp r1, r2
+ beq exit_wakeup
+
+ /* Sleep wakeup reset */
+ ldr r2, =S5P_CHECK_SLEEP
+ cmp r1, r2
+ beq wakeup_reset
+
+ /*
+ * If U-boot is already running in ram, no need to relocate U-Boot.
+ * Memory controller must be configured before relocating U-Boot
+ * in ram.
+ */
+ ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
+ bic r1, pc, r0 /* pc <- current addr of code */
+ /* r1 <- unmasked bits of pc */
+ ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
+ bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
+ cmp r1, r2 /* compare r1, r2 */
+ beq 1f /* r0 == r1 then skip sdram init */
+
+ /* init system clock */
+ bl system_clock_init
+
+ /* Memory initialize */
+ bl mem_ctrl_asm_init
+
+1:
+ /* for UART */
+ bl uart_asm_init
+ bl tzpc_init
+ pop {pc}
+
+wakeup_reset:
+ bl system_clock_init
+ bl mem_ctrl_asm_init
+ bl tzpc_init
+
+exit_wakeup:
+ /* Load return address and jump to kernel */
+ ldr r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
+
+ /* r1 = physical address of exynos5_cpu_resume function*/
+ ldr r1, [r0]
+
+ /* Jump to kernel */
+ mov pc, r1
+ nop
+ nop
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+ push {lr}
+ ldr r0, =EXYNOS5_CLOCK_BASE
+
+ /*
+ * MUX_APLL_SEL[0]: FINPLL = 0
+ * MUX_CPU_SEL[6]: MOUTAPLL = 0
+ * MUX_HPM_SEL[20]: MOUTAPLL = 0
+ */
+ ldr r1, =0x0
+ ldr r2, =CLK_SRC_CPU_OFFSET
+ str r1, [r0, r2]
+
+ /* MUX_MPLL_SEL[8]: FINPLL = 0 */
+ ldr r1, =0x0
+ ldr r2, =CLK_SRC_CORE1_OFFSET
+ str r1, [r0, r2]
+
+ /*
+ * VPLLSRC_SEL[0]: FINPLL = 0
+ * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
+ */
+ ldr r1, =0x0
+ ldr r2, =CLK_SRC_TOP2_OFFSET
+ str r1, [r0, r2]
+
+ /* MUX_BPLL_SEL[0]: FINPLL = 0*/
+ ldr r1, =0x0
+ ldr r2, =CLK_SRC_CDREX_OFFSET
+ str r1, [r0, r2]
+
+ /* MUX_ACLK_* Clock Selection */
+ ldr r1, =CLK_SRC_TOP0_VAL
+ ldr r2, =CLK_SRC_TOP0_OFFSET
+ str r1, [r0, r2]
+
+ /* MUX_ACLK_* Clock Selection */
+ ldr r1, =CLK_SRC_TOP1_VAL
+ ldr r2, =CLK_SRC_TOP1_OFFSET
+ str r1, [r0, r2]
+
+
+ /* MUX_ACLK_* Clock Selection */
+ ldr r1, =CLK_SRC_TOP3_VAL
+ ldr r2, =CLK_SRC_TOP3_OFFSET
+ str r1, [r0, r2]
+
+ /* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
+ ldr r1, =CLK_SRC_CORE0_VAL
+ ldr r2, =CLK_SRC_CORE0_OFFSET
+ str r1, [r0, r2]
+
+ /* MUX_ATCLK_LEX[0]: ACLK_200 = 0*/
+ ldr r1, =CLK_SRC_LEX_VAL
+ ldr r2, =CLK_SRC_LEX_OFFSET
+ str r1, [r0, r2]
+
+
+ /* UART [0-5]: SCLKMPLL = 6 */
+ ldr r1, =CLK_SRC_PERIC0_VAL
+ ldr r2, =CLK_SRC_PERIC0_OFFSET
+ str r1, [r0, r2]
+
+ /* Set Clock Ratios */
+ ldr r1, =CLK_DIV_CPU0_VAL
+ ldr r2, =CLK_DIV_CPU0_OFFSET
+ str r1, [r0, r2]
+
+ /* Set COPY and HPM Ratio */
+ ldr r1, =CLK_DIV_CPU1_VAL
+ ldr r2, =CLK_DIV_CPU1_OFFSET
+ str r1, [r0, r2]
+
+ /* CORED_RATIO, COREP_RATIO */
+ ldr r1, =CLK_DIV_CORE0_VAL
+ ldr r2, =CLK_DIV_CORE0_OFFSET
+ str r1, [r0, r2]
+
+ /* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
+ ldr r1, =CLK_DIV_CORE1_VAL
+ ldr r2, =CLK_DIV_CORE1_OFFSET
+ str r1, [r0, r2]
+
+ /* ACLK_*_RATIO */
+ ldr r1, =CLK_DIV_TOP0_VAL
+ ldr r2, =CLK_DIV_TOP0_OFFSET
+ str r1, [r0, r2]
+
+ /* ACLK_*_RATIO */
+ ldr r1, =CLK_DIV_TOP1_VAL
+ ldr r2, =CLK_DIV_TOP1_OFFSET
+ str r1, [r0, r2]
+
+ /* CDREX Ratio */
+ ldr r1, =CLK_DIV_CDREX_VAL
+ ldr r2, =CLK_DIV_CDREX_OFFSET
+ str r1, [r0, r2]
+
+ /* MCLK_EFPHY_RATIO[3:0] */
+ ldr r1, =CLK_DIV_CDREX2_VAL
+ ldr r2, =CLK_DIV_CDREX2_OFFSET
+ str r1, [r0, r2]
+
+ /* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
+ ldr r1, =CLK_DIV_LEX_VAL
+ ldr r2, =CLK_DIV_LEX_OFFSET
+ str r1, [r0, r2]
+
+ /* PCLK_R0X_RATIO[3:0] */
+ ldr r1, =CLK_DIV_R0X_VAL
+ ldr r2, =CLK_DIV_R0X_OFFSET
+ str r1, [r0, r2]
+
+ /* PCLK_R1X_RATIO[3:0] */
+ ldr r1, =CLK_DIV_R1X_VAL
+ ldr r2, =CLK_DIV_R1X_OFFSET
+ str r1, [r0, r2]
+
+ /* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
+ ldr r1, =CLK_SRC_FSYS_VAL
+ ldr r2, =CLK_SRC_FSYS_OFFSET
+ str r1, [r0, r2]
+
+ /* UART[0-4] */
+ ldr r1, =CLK_DIV_PERIC0_VAL
+ ldr r2, =CLK_DIV_PERIC0_OFFSET
+ str r1, [r0, r2]
+
+ /* PWM_RATIO[3:0] */
+ ldr r1, =CLK_DIV_PERIC3_VAL
+ ldr r2, =CLK_DIV_PERIC3_OFFSET
+ str r1, [r0, r2]
+
+ /* SATA_RATIO, USB_DRD_RATIO */
+ ldr r1, =CLK_DIV_FSYS0_VAL
+ ldr r2, =CLK_DIV_FSYS0_OFFSET
+ str r1, [r0, r2]
+
+ /* MMC[0-1] */
+ ldr r1, =CLK_DIV_FSYS1_VAL
+ ldr r2, =CLK_DIV_FSYS1_OFFSET
+ str r1, [r0, r2]
+
+ /* MMC[2-3] */
+ ldr r1, =CLK_DIV_FSYS2_VAL
+ ldr r2, =CLK_DIV_FSYS2_OFFSET
+ str r1, [r0, r2]
+
+ /* MMC[4] */
+ ldr r1, =CLK_DIV_FSYS3_VAL
+ ldr r2, =CLK_DIV_FSYS3_OFFSET
+ str r1, [r0, r2]
+
+ /* ACLK|PLCK_ACP_RATIO */
+ ldr r1, =CLK_DIV_ACP_VAL
+ ldr r2, =CLK_DIV_ACP_OFFSET
+ str r1, [r0, r2]
+
+ /* ISPDIV0_RATIO, ISPDIV1_RATIO */
+ ldr r1, =CLK_DIV_ISP0_VAL
+ ldr r2, =CLK_DIV_ISP0_OFFSET
+ str r1, [r0, r2]
+
+ /* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
+ ldr r1, =CLK_DIV_ISP1_VAL
+ ldr r2, =CLK_DIV_ISP1_OFFSET
+ str r1, [r0, r2]
+
+ /* MPWMDIV_RATIO */
+ ldr r1, =CLK_DIV_ISP2_VAL
+ ldr r2, =CLK_DIV_ISP2_OFFSET
+ str r1, [r0, r2]
+
+ /* PLL locktime */
+ ldr r1, =APLL_LOCK_VAL
+ ldr r2, =APLL_LOCK_OFFSET
+ str r1, [r0, r2]
+
+ ldr r1, =MPLL_LOCK_VAL
+ ldr r2, =MPLL_LOCK_OFFSET
+ str r1, [r0, r2]
+
+ ldr r1, =BPLL_LOCK_VAL
+ ldr r2, =BPLL_LOCK_OFFSET
+ str r1, [r0, r2]
+
+ ldr r1, =CPLL_LOCK_VAL
+ ldr r2, =CPLL_LOCK_OFFSET
+ str r1, [r0, r2]
+
+ ldr r1, =EPLL_LOCK_VAL
+ ldr r2, =EPLL_LOCK_OFFSET
+ str r1, [r0, r2]
+
+ ldr r1, =VPLL_LOCK_VAL
+ ldr r2, =VPLL_LOCK_OFFSET
+ str r1, [r0, r2]
+
+ mov r1, #0x10000
+2: subs r1, r1, #1
+ bne 2b
+
+
+ /* Set APLL */
+ ldr r1, =APLL_CON1_VAL
+ ldr r2, =APLL_CON1_OFFSET
+ str r1, [r0, r2]
+ ldr r1, =APLL_CON0_VAL
+ ldr r2, =APLL_CON0_OFFSET
+ str r1, [r0, r2]
+
+ mov r1, #0x30000
+3: subs r1, r1, #1
+ bne 3b
+
+ /* Set MPLL */
+ ldr r1, =MPLL_CON1_VAL
+ ldr r2, =MPLL_CON1_OFFSET
+ str r1, [r0, r2]
+ ldr r1, =MPLL_CON0_VAL
+ ldr r2, =MPLL_CON0_OFFSET
+ str r1, [r0, r2]
+
+ /* wait ?us */
+ mov r1, #0x30000
+4: subs r1, r1, #1
+ bne 4b
+
+ /* Set BPLL */
+ ldr r1, =BPLL_CON1_VAL
+ ldr r2, =BPLL_CON1_OFFSET
+ str r1, [r0, r2]
+ ldr r1, =BPLL_CON0_VAL
+ ldr r2, =BPLL_CON0_OFFSET
+ str r1, [r0, r2]
+
+ /* wait ?us */
+ mov r1, #0x30000
+5: subs r1, r1, #1
+ bne 5b
+
+ /* Set CPLL */
+ ldr r1, =CPLL_CON1_VAL
+ ldr r2, =CPLL_CON1_OFFSET
+ str r1, [r0, r2]
+ ldr r1, =CPLL_CON0_VAL
+ ldr r2, =CPLL_CON0_OFFSET
+ str r1, [r0, r2]
+
+ /* wait ?us */
+ mov r1, #0x30000
+6: subs r1, r1, #1
+ bne 6b
+
+ /* Set EPLL */
+ ldr r1, =EPLL_CON2_VAL
+ ldr r2, =EPLL_CON2_OFFSET
+ str r1, [r0, r2]
+ ldr r1, =EPLL_CON1_VAL
+ ldr r2, =EPLL_CON1_OFFSET
+ str r1, [r0, r2]
+ ldr r1, =EPLL_CON0_VAL
+ ldr r2, =EPLL_CON0_OFFSET
+ str r1, [r0, r2]
+
+ /* wait ?us */
+ mov r1, #0x30000
+7: subs r1, r1, #1
+ bne 7b
+
+ /* Set VPLL */
+ ldr r1, =VPLL_CON2_VAL
+ ldr r2, =VPLL_CON2_OFFSET
+ str r1, [r0, r2]
+ ldr r1, =VPLL_CON1_VAL
+ ldr r2, =VPLL_CON1_OFFSET
+ str r1, [r0, r2]
+ ldr r1, =VPLL_CON0_VAL
+ ldr r2, =VPLL_CON0_OFFSET
+ str r1, [r0, r2]
+
+ /* wait ?us */
+ mov r1, #0x30000
+8: subs r1, r1, #1
+ bne 8b
+
+ /* After Initiallising th PLL select the sources accordingly */
+ /* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
+ ldr r1, =CLK_SRC_CPU_VAL
+ ldr r2, =CLK_SRC_CPU_OFFSET
+ str r1, [r0, r2]
+
+ /* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
+ ldr r1, =CLK_SRC_CORE1_VAL
+ ldr r2, =CLK_SRC_CORE1_OFFSET
+ str r1, [r0, r2]
+
+ /* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
+ ldr r1, =CLK_SRC_CDREX_VAL
+ ldr r2, =CLK_SRC_CDREX_OFFSET
+ str r1, [r0, r2]
+
+ /*
+ * VPLLSRC_SEL[0]: FINPLL = 0
+ * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
+ * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
+ */
+ ldr r1, =CLK_SRC_TOP2_VAL
+ ldr r2, =CLK_SRC_TOP2_OFFSET
+ str r1, [r0, r2]
+
+ pop {pc}
+
+
+/*
+ * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
+ * void uart_asm_init(void)
+ */
+ .globl uart_asm_init
+uart_asm_init:
+
+ /* setup UART0-UART3 GPIOs (part1) */
+ mov r0, r7
+ ldr r1, =EXYNOS5_GPIO_A0_CON_VAL
+ str r1, [r0, #EXYNOS5_GPIO_A0_CON_OFFSET]
+ ldr r1, =EXYNOS5_GPIO_A1_CON_VAL
+ str r1, [r0, #EXYNOS5_GPIO_A1_CON_OFFSET]
+
+ ldr r0, =EXYNOS5_UART_BASE
+ add r0, r0, #EXYNOS5_DEFAULT_UART_OFFSET
+
+ ldr r1, =ULCON_VAL
+ str r1, [r0, #ULCON_OFFSET]
+ ldr r1, =UCON_VAL
+ str r1, [r0, #UCON_OFFSET]
+ ldr r1, =UFCON_VAL
+ str r1, [r0, #UFCON_OFFSET]
+ ldr r1, =UBRDIV_VAL
+ str r1, [r0, #UBRDIV_OFFSET]
+ ldr r1, =UFRACVAL_VAL
+ str r1, [r0, #UFRACVAL_OFFSET]
+ ldr r1, =0x4f
+ str r1, [r0, #UTXH_OFFSET] @'O'
+ mov pc, lr
+ nop
+ nop
+ nop
+
+/* Setting TZPC[TrustZone Protection Controller] */
+tzpc_init:
+
+ ldr r0, =TZPC0_BASE
+ mov r1, #R0SIZE
+ str r1, [r0]
+ mov r1, #DECPROTXSET
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC1_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC2_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC3_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC4_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC5_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC6_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC7_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC8_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC9_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+
+ mov pc, lr
diff --git a/board/samsung/smdk5250/mem_setup.S b/board/samsung/smdk5250/mem_setup.S
new file mode 100644
index 0000000..a7cc54b
--- /dev/null
+++ b/board/samsung/smdk5250/mem_setup.S
@@ -0,0 +1,600 @@
+/*
+ * Memory setup for SMDK5250 board based on EXYNOS5
+ *
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <config.h>
+#include "smdk5250_setup.h"
+/* APLL : 1GHz */
+/* MCLK_CDREX: MCLK_CDREX_533*/
+/* LPDDR support: LPDDR2 */
+
+/* (Memory Interleaving Size = 1 << IV_SIZE) */
+#define CONFIG_IV_SIZE 0x07
+#define RD_LVL 1
+
+ .globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+ push {lr}
+
+ /* CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC */
+ ldr r0, =EXYNOS5_CLOCK_BASE
+
+ /* Reset PHY Controllor */
+ ldr r1, =0x0
+ ldr r2, =LPDDR3PHY_CTRL
+ str r1, [r0, r2]
+
+ bl delay
+
+ /*set Read Latance and Burst Length for PHY0 and PHY1 */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x408
+ str r1, [r0, #DMC_PHY_CON42]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x408
+ str r1, [r0, #DMC_PHY_CON42]
+
+ /*
+ * ZQ Calibration:
+ * Select Driver Strength,
+ * long calibration for manual calibration
+ */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x0DA40304
+ str r1, [r0, #DMC_PHY_CON16]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x0DA40304
+ str r1, [r0, #DMC_PHY_CON16]
+
+ /* Enable termination */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x0DAC0304
+ str r1, [r0, #DMC_PHY_CON16]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x0DAC0304
+ str r1, [r0, #DMC_PHY_CON16]
+
+ /* Start Manual Calibration */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x0DAC0306
+ str r1, [r0, #DMC_PHY_CON16]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x0DAC0306
+ str r1, [r0, #DMC_PHY_CON16]
+
+ bl delay
+
+ /* Enable termination */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x0DAC0304
+ str r1, [r0, #DMC_PHY_CON16]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x0DAC0304
+ str r1, [r0, #DMC_PHY_CON16]
+
+ /* DDR Mode: LPDDR2 */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x17021240
+ str r1, [r0, #DMC_PHY_CON0]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x17021240
+ str r1, [r0, #DMC_PHY_CON0]
+
+ /* DQS, DQ: Signal, for LPDDR2: Always Set */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x00000F0F
+ str r1, [r0, #DMC_PHY_CON14]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x00000F0F
+ str r1, [r0, #DMC_PHY_CON14]
+
+ /* RD_FETCH: 1 */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x1FFF1000
+ str r1, [r0, #DMC_CONCONTROL]
+ bl delay
+
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x0FFF1000
+ str r1, [r0, #DMC_CONCONTROL]
+
+ bl delay
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000008
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ /* Reset Force DLL Resyncronization */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000000
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 4
+ * Number of chips: 2
+ * Memory Bus width: 32 bit
+ * Memory Type: LPDDR2-S4
+ * Additional Latancy for PLL: 1 Cycle
+ */
+ ldr r1, =0x00212500
+ str r1, [r0, #DMC_MEMCONTROL]
+
+ /*
+ * Memory Configuration Chip 0
+ * Address Mapping: Interleaved
+ * Number of Column address Bits: 10 bits
+ * Number of Rows Address Bits: 14
+ * Number of Banks: 8
+ */
+ ldr r1, =0x00001323
+ str r1, [r0, #DMC_MEMCONFIG0]
+
+ /*
+ * Memory Configuration Chip 1
+ * Address Mapping: Interleaved
+ * Number of Column address Bits: 10 bits
+ * Number of Rows Address Bits: 14
+ * Number of Banks: 8
+ */
+ ldr r1, =0x00001323
+ str r1, [r0, #DMC_MEMCONFIG1]
+
+ /*
+ * Chip0: AXI
+ * AXI Base Address: 0x40000000
+ * AXI Base Address Mask: 0x780
+ */
+ ldr r1, =0x00400780
+ str r1, [r0, #DMC_MEMBASECONFIG0]
+
+ /*
+ * Chip1: AXI
+ * AXI Base Address: 0x80000000
+ * AXI Base Address Mask: 0x780
+ */
+ ldr r1, =0x00800780
+ str r1, [r0, #DMC_MEMBASECONFIG1]
+
+ /* Precharge Configuration */
+ ldr r1, =0xFF000000
+ str r1, [r0, #DMC_PRECHCONFIG]
+
+ /* Power Down mode Configuration */
+ ldr r1, =0xFFFF00FF
+ str r1, [r0, #DMC_PWRDNCONFIG]
+
+ /* Periodic Refrese Interval */
+ ldr r1, =0x0000005D
+ str r1, [r0, #DMC_TIMINGAREF]
+
+ /* MCLK_CDREX_533 */
+ /*
+ * TimingRow, TimingData, TimingPower Setting:
+ * Values as per Memory AC Parameters
+ */
+ ldr r1, =0x2336544C
+ str r1, [r0, #DMC_TIMINGROW]
+
+ ldr r1, =0x24202408
+ str r1, [r0, #DMC_TIMINGDATA]
+
+ ldr r1, =0x38260235
+ str r1, [r0, #DMC_TIMINGPOWER]
+
+ /* Memory Channel Inteleaving Size: 128 Bytes */
+ ldr r1, =CONFIG_IV_SIZE
+ str r1, [r0, #DMC_IVCONTROL]
+
+ /* Set Offsets to read DQS */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x7F7F7F7F
+ str r1, [r0, #DMC_PHY_CON4]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x7F7F7F7F
+ str r1, [r0, #DMC_PHY_CON4]
+
+ /* Set Offsets to read DQ */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x7F7F7F7F
+ str r1, [r0, #DMC_PHY_CON6]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x7F7F7F7F
+ str r1, [r0, #DMC_PHY_CON6]
+
+ /* Debug Offset */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x0000007F
+ str r1, [r0, #DMC_PHY_CON10]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x0000007F
+ str r1, [r0, #DMC_PHY_CON10]
+
+ /* Start DLL Locking */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x10107F50
+ str r1, [r0, #DMC_PHY_CON12]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x10107F50
+ str r1, [r0, #DMC_PHY_CON12]
+
+ bl delay
+
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000008
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ /* Reset DLL Resyncronization */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000000
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ /*
+ * NOP CMD: Channel 0, Chip 0
+ * Exit from active/precharge power down or deep power down
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x07000000
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ ldr r1, =0x00071C00
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ ldr r1, =0x00010BFC
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* MCLK_CDREX_533 */
+ ldr r1, =0x00000708
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ ldr r1, =0x00000818
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /*
+ * NOP CMD: Channel 0, Chip 1
+ * Exit from active/precharge power down or deep power down
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x07100000
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ ldr r1, =0x00171C00
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ ldr r1, =0x00110BFC
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* MCLK_CDREX_533 */
+ ldr r1, =0x00100708
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ ldr r1, =0x00100818
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /*
+ * NOP CMD: Channel 1, Chip 0
+ * Exit from active/precharge power down or deep power down
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x17000000
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ ldr r1, =0x10071C00
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ ldr r1, =0x10010BFC
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* MCLK_CDREX_533 */
+ ldr r1, =0x10000708
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ ldr r1, =0x10000818
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /*
+ * NOP CMD: Channel 1, Chip 1
+ * Exit from active/precharge power down or deep power down
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x17100000
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ ldr r1, =0x10171C00
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ ldr r1, =0x10110BFC
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* MCLK_CDREX_533 */
+ ldr r1, =0x10100708
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ ldr r1, =0x10100818
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* Reset DQS Offsets */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x08080808
+ str r1, [r0, #DMC_PHY_CON4]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x08080808
+ str r1, [r0, #DMC_PHY_CON4]
+
+ /* Reset DQ Offsets */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x08080808
+ str r1, [r0, #DMC_PHY_CON6]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x08080808
+ str r1, [r0, #DMC_PHY_CON6]
+
+ /* Reset debug Offsets */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x00000008
+ str r1, [r0, #DMC_PHY_CON10]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x00000008
+ str r1, [r0, #DMC_PHY_CON10]
+
+ /* Set DLL Locking */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x10107F30
+ str r1, [r0, #DMC_PHY_CON12]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x10107F30
+ str r1, [r0, #DMC_PHY_CON12]
+
+ bl delay
+
+ /* Start DLL Locking */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x10107F70
+ str r1, [r0, #DMC_PHY_CON12]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x10107F70
+ str r1, [r0, #DMC_PHY_CON12]
+
+ bl delay
+
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000008
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ /* Reset DLL Resyncronization */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000000
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ bl delay
+
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000008
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ /* Reset DLL Resyncronization */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000000
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ bl delay
+#if defined(RD_LVL)
+ /* DLL On */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x10102D50
+ str r1, [r0, #DMC_PHY_CON12]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x10102D50
+ str r1, [r0, #DMC_PHY_CON12]
+
+ /*
+ * Set ctrl_gateadj, ctrl_readadj
+ * ctrl_gateduradj, rdlvl_pass_adj
+ * rdlvl_rddataPadj
+ */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x09210001
+ str r1, [r0, #DMC_PHY_CON1]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x09210001
+ str r1, [r0, #DMC_PHY_CON1]
+
+ /* LPDDR2 Address */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x00000208
+ str r1, [r0, #DMC_PHY_CON22]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x00000208
+ str r1, [r0, #DMC_PHY_CON22]
+
+ /* Enable Byte Read Leleling */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x17023240
+ str r1, [r0, #DMC_PHY_CON0]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x17023240
+ str r1, [r0, #DMC_PHY_CON0]
+
+ /* rdlvl_en: Use levelling offset instead ctrl_shiftc */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x02010004
+ str r1, [r0, #DMC_PHY_CON2]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x02010004
+ str r1, [r0, #DMC_PHY_CON2]
+
+ bl delay
+
+ /* Enable Data Eye Trainig */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000002
+ str r1, [r0, #DMC_RDLVL_CONFIG]
+
+ bl delay
+
+ /* Disable Data Eye Trainig */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000000
+ str r1, [r0, #DMC_RDLVL_CONFIG]
+
+ /* RdDeSkew_clear: Clear */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x02012004
+ str r1, [r0, #DMC_PHY_CON2]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x02012004
+ str r1, [r0, #DMC_PHY_CON2]
+
+ /* Start DLL Locking */
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x10107F70
+ str r1, [r0, #DMC_PHY_CON12]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x10107F70
+ str r1, [r0, #DMC_PHY_CON12]
+
+ /* Force DLL Resyncronization */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000008
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ /* Reset DLL Resyncronization */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00000000
+ str r1, [r0, #DMC_PHYCONTROL0]
+
+ bl delay
+
+ /* ctrl_atgate: ctrl_gate_p*, ctrl_read_p* generated by PHY*/
+ ldr r0, =EXYNOS5_PHY0_CTRL_BASE
+ ldr r1, =0x17023200
+ str r1, [r0, #DMC_PHY_CON0]
+ ldr r0, =EXYNOS5_PHY1_CTRL_BASE
+ ldr r1, =0x17023200
+ str r1, [r0, #DMC_PHY_CON0]
+
+ /* Channel:0, Chip:0, PALL (all banks precharge) CMD */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x01000000
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* Channel:0, Chip:1, PALL (all banks precharge) CMD */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x01100000
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* Channel:1, Chip:0, PALL (all banks precharge) CMD */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x11000000
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+
+ /* Channel:1, Chip:1, PALL (all banks precharge) CMD */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x11100000
+ str r1, [r0, #DMC_DIRECTCMD]
+
+ bl delay
+#endif
+ /*
+ * Dynamic Clock: Stops During Idle Period
+ * Dynamic Power Down: Enable
+ * Dynamic Self refresh: Enable
+ * Memory Burst length: 4
+ * Number of chips: 2
+ * Memory Bus width: 32 bit
+ * Memory Type: LPDDR2-S4
+ * Additional Latancy for PLL: 1 Cycle
+ */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x00212523
+ str r1, [r0, #DMC_MEMCONTROL]
+
+ /* Start Auto refresh */
+ ldr r0, =EXYNOS5_DMC_CTRL_BASE
+ ldr r1, =0x0FFF10E0
+ str r1, [r0, #DMC_CONCONTROL]
+
+ pop {lr}
+ mov pc, lr
+
+delay:
+ mov r2, #0x10000
+delayloop:
+ subs r2, r2, #1
+ bne delayloop
+ mov pc, lr
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
new file mode 100644
index 0000000..0ea9a32
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sromc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct exynos5_gpio_part1 *gpio1;
+
+int board_init(void)
+{
+ gpio1 = (struct exynos5_gpio_part1 *) EXYNOS5_GPIO_PART1_BASE;
+
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
+ PHYS_SDRAM_1_SIZE);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
+ PHYS_SDRAM_2_SIZE);
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
+ PHYS_SDRAM_3_SIZE);
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
+ PHYS_SDRAM_4_SIZE);
+ gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
+ gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5, \
+ PHYS_SDRAM_5_SIZE);
+ gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
+ gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6, \
+ PHYS_SDRAM_6_SIZE);
+ gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
+ gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7, \
+ PHYS_SDRAM_7_SIZE);
+ gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
+ gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8, \
+ PHYS_SDRAM_8_SIZE);
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("\nBoard: SMDK5250\n");
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int i, err;
+
+ /*
+ * MMC2 SD card GPIO:
+ *
+ * GPC2[0] SD_2_CLK(2)
+ * GPC2[1] SD_2_CMD(2)
+ * GPC2[2] SD_2_CDn
+ * GPC2[3:6] SD_2_DATA[0:3](2)
+ */
+ for (i = 0; i < 7; i++) {
+ /* GPC2[0:6] special function 2 */
+ s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2));
+
+ /* GPK2[0:6] drv 4x */
+ s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X);
+
+ /* GPK2[0:1] pull disable */
+ if (i == 0 || i == 1) {
+ s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE);
+ continue;
+ }
+
+ /* GPK2[2:6] pull up */
+ s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP);
+ }
+
+ err = s5p_mmc_init(2, 4);
+ return err;
+}
+#endif
diff --git a/board/samsung/smdk5250/smdk5250_setup.h b/board/samsung/smdk5250/smdk5250_setup.h
new file mode 100644
index 0000000..9d0ce0d
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250_setup.h
@@ -0,0 +1,589 @@
+/*
+ * Machine Specific Values for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SMDK5250_SETUP_H
+#define _SMDK5250_SETUP_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* Offsets of clock registers (sources and dividers) */
+#define CLK_SRC_CPU_OFFSET 0x00200
+#define CLK_DIV_CPU0_OFFSET 0x00500
+#define CLK_DIV_CPU1_OFFSET 0x00504
+
+#define CLK_SRC_CORE0_OFFSET 0x04200
+#define CLK_DIV_CORE0_OFFSET 0x04500
+
+#define CLK_SRC_CORE1_OFFSET 0x04204
+#define CLK_DIV_CORE1_OFFSET 0x04504
+
+#define CLK_SRC_TOP0_OFFSET 0x10210
+#define CLK_SRC_TOP1_OFFSET 0x10214
+#define CLK_SRC_TOP2_OFFSET 0x10218
+#define CLK_SRC_TOP3_OFFSET 0x1021C
+#define CLK_DIV_TOP0_OFFSET 0x10510
+#define CLK_DIV_TOP1_OFFSET 0x10514
+
+#define CLK_SRC_FSYS_OFFSET 0x10244
+#define CLK_DIV_FSYS0_OFFSET 0x10548
+#define CLK_DIV_FSYS1_OFFSET 0x1054C
+#define CLK_DIV_FSYS2_OFFSET 0x10550
+#define CLK_DIV_FSYS3_OFFSET 0x10554
+
+#define CLK_SRC_PERIC0_OFFSET 0x10250
+#define CLK_DIV_PERIC0_OFFSET 0x10558
+#define CLK_DIV_PERIC3_OFFSET 0x10564
+
+#define CLK_SRC_LEX_OFFSET 0x14200
+#define CLK_DIV_LEX_OFFSET 0x14500
+
+#define CLK_DIV_R0X_OFFSET 0x18500
+#define CLK_DIV_R1X_OFFSET 0x1C500
+
+
+#define CLK_SRC_CDREX_OFFSET 0x20200
+#define CLK_DIV_CDREX_OFFSET 0x20500
+#define CLK_DIV_CDREX2_OFFSET 0x20504
+
+#define CLK_DIV_ACP_OFFSET 0x08500
+#define CLK_DIV_ISP0_OFFSET 0x0C300
+#define CLK_DIV_ISP1_OFFSET 0x0C304
+#define CLK_DIV_ISP2_OFFSET 0x0C308
+
+
+#define APLL_LOCK_OFFSET 0x00000
+#define MPLL_LOCK_OFFSET 0x04000
+#define APLL_CON0_OFFSET 0x00100
+#define APLL_CON1_OFFSET 0x00104
+#define MPLL_CON0_OFFSET 0x04100
+#define MPLL_CON1_OFFSET 0x04104
+
+#define BPLL_LOCK_OFFSET 0x20010
+#define BPLL_CON0_OFFSET 0x20110
+#define BPLL_CON1_OFFSET 0x20114
+
+#define CPLL_LOCK_OFFSET 0x10020
+#define EPLL_LOCK_OFFSET 0x10030
+#define VPLL_LOCK_OFFSET 0x10040
+
+#define CPLL_CON0_OFFSET 0x10120
+#define CPLL_CON1_OFFSET 0x10124
+
+#define EPLL_CON0_OFFSET 0x10130
+#define EPLL_CON1_OFFSET 0x10134
+#define EPLL_CON2_OFFSET 0x10138
+
+#define VPLL_CON0_OFFSET 0x10140
+#define VPLL_CON1_OFFSET 0x10144
+#define VPLL_CON2_OFFSET 0x10148
+
+
+/* DMC: DRAM Controllor Register offsets */
+#define DMC_CONCONTROL 0x00
+#define DMC_MEMCONTROL 0x04
+#define DMC_MEMCONFIG0 0x08
+#define DMC_MEMCONFIG1 0x0C
+#define DMC_DIRECTCMD 0x10
+#define DMC_PRECHCONFIG 0x14
+#define DMC_PHYCONTROL0 0x18
+#define DMC_PWRDNCONFIG 0x28
+#define DMC_TIMINGAREF 0x30
+#define DMC_TIMINGROW 0x34
+#define DMC_TIMINGDATA 0x38
+#define DMC_TIMINGPOWER 0x3C
+#define DMC_IVCONTROL 0xF0
+#define DMC_RDLVL_CONFIG 0xF8
+#define DMC_MEMBASECONFIG0 0x010C
+#define DMC_MEMBASECONFIG1 0x0110
+#define LPDDR3PHY_CTRL 0x20A10
+
+#define DMC_PHY_CON0 0x00
+#define DMC_PHY_CON1 0x04
+#define DMC_PHY_CON10 0x28
+#define DMC_PHY_CON12 0x30
+#define DMC_PHY_CON14 0x38
+#define DMC_PHY_CON16 0x40
+#define DMC_PHY_CON2 0x08
+#define DMC_PHY_CON22 0x5C
+#define DMC_PHY_CON4 0x10
+#define DMC_PHY_CON42 0xAC
+#define DMC_PHY_CON6 0x18
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET 0x800
+#define INFORM1_OFFSET 0x804
+
+/* GPIO Offsets for UART: GPIO Contol Register */
+#define EXYNOS5_GPIO_A0_CON_OFFSET 0x0
+#define EXYNOS5_GPIO_A1_CON_OFFSET 0x20
+
+/* UART Register offsets */
+#define ULCON_OFFSET 0x00
+#define UCON_OFFSET 0x04
+#define UFCON_OFFSET 0x08
+#define UBRDIV_OFFSET 0x28
+#define UFRACVAL_OFFSET 0x2C
+#define UTXH_OFFSET 0x20
+
+/* TZPC : Register Offsets */
+#define TZPC0_BASE 0x10100000
+#define TZPC1_BASE 0x10110000
+#define TZPC2_BASE 0x10120000
+#define TZPC3_BASE 0x10130000
+#define TZPC4_BASE 0x10140000
+#define TZPC5_BASE 0x10150000
+#define TZPC6_BASE 0x10160000
+#define TZPC7_BASE 0x10170000
+#define TZPC8_BASE 0x10180000
+#define TZPC9_BASE 0x10190000
+
+#define TZPC_DECPROT0SET_OFFSET 0x804
+#define TZPC_DECPROT1SET_OFFSET 0x810
+#define TZPC_DECPROT2SET_OFFSET 0x81C
+#define TZPC_DECPROT3SET_OFFSET 0x828
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 0
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
+
+/* CLK_DIV_CPU0 */
+#define ARM2_RATIO 0x0
+#define APLL_RATIO 0x1
+#define PCLK_DBG_RATIO 0x1
+#define ATB_RATIO 0x4
+#define PERIPH_RATIO 0x7
+#define ACP_RATIO 0x7
+#define CPUD_RATIO 0x2
+#define ARM_RATIO 0x0
+#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
+ | (APLL_RATIO << 24) \
+ | (PCLK_DBG_RATIO << 20) \
+ | (ATB_RATIO << 16) \
+ | (PERIPH_RATIO << 12) \
+ | (ACP_RATIO << 8) \
+ | (CPUD_RATIO << 4) \
+ | (ARM_RATIO))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO 0x4
+#define COPY_RATIO 0x0
+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
+ | (COPY_RATIO))
+
+#define APLL_MDIV 0x7D
+#define APLL_PDIV 0x3
+#define APLL_SDIV 0x0
+
+#define MPLL_MDIV 0x64
+#define MPLL_PDIV 0x3
+#define MPLL_SDIV 0x0
+
+#define CPLL_MDIV 0x96
+#define CPLL_PDIV 0x4
+#define CPLL_SDIV 0x0
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL (0x00203800)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x00203800)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL (0x00203800)
+
+#define EPLL_MDIV 0x60
+#define EPLL_PDIV 0x3
+#define EPLL_SDIV 0x3
+
+#define EPLL_CON1_VAL 0x00000000
+#define EPLL_CON2_VAL 0x00000080
+
+#define VPLL_MDIV 0x96
+#define VPLL_PDIV 0x3
+#define VPLL_SDIV 0x2
+
+#define VPLL_CON1_VAL 0x00000000
+#define VPLL_CON2_VAL 0x00000080
+
+#define BPLL_MDIV 0x215
+#define BPLL_PDIV 0xC
+#define BPLL_SDIV 0x1
+
+#define BPLL_CON1_VAL 0x00203800
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+#define APLL_CON0_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+#define MPLL_CON0_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+#define CPLL_CON0_VAL set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
+#define EPLL_CON0_VAL set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+#define VPLL_CON0_VAL set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+#define BPLL_CON0_VAL set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
+
+/* CLK_SRC_CORE0 */
+#define CLK_SRC_CORE0_VAL 0x00060000
+
+/* CLK_SRC_CORE1 */
+#define CLK_SRC_CORE1_VAL 0x100
+
+/* CLK_DIV_CORE0 */
+#define CLK_DIV_CORE0_VAL 0x120000
+
+/* CLK_DIV_CORE1 */
+#define CLK_DIV_CORE1_VAL 0x07070700
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL 0x111
+
+/* CLK_DIV_CDREX */
+#define MCLK_CDREX2_RATIO 0x0
+#define ACLK_EFCON_RATIO 0x1
+#define MCLK_DPHY_RATIO 0x0
+#define MCLK_CDREX_RATIO 0x0
+#define ACLK_C2C_200_RATIO 0x1
+#define C2C_CLK_400_RATIO 0x1
+#define PCLK_CDREX_RATIO 0x3
+#define ACLK_CDREX_RATIO 0x1
+#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 20) \
+ | (MCLK_CDREX_RATIO << 16) \
+ | (ACLK_C2C_200_RATIO << 12) \
+ | (C2C_CLK_400_RATIO << 8) \
+ | (PCLK_CDREX_RATIO << 4) \
+ | (ACLK_CDREX_RATIO))
+
+#define MCLK_EFPHY_RATIO 0x4
+#define CLK_DIV_CDREX2_VAL MCLK_EFPHY_RATIO
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL 0x12
+
+/* CLK_SRC_TOP0 */
+#define MUX_ACLK_300_GSCL_SEL 0x1
+#define MUX_ACLK_300_GSCL_MID_SEL 0x0
+#define MUX_ACLK_400_SEL 0x0
+#define MUX_ACLK_333_SEL 0x0
+#define MUX_ACLK_300_DISP1_SEL 0x1
+#define MUX_ACLK_300_DISP1_MID_SEL 0x0
+#define MUX_ACLK_200_SEL 0x0
+#define MUX_ACLK_166_SEL 0x0
+#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
+ | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
+ | (MUX_ACLK_400_SEL << 20) \
+ | (MUX_ACLK_333_SEL << 16) \
+ | (MUX_ACLK_300_DISP1_SEL << 15) \
+ | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
+ | (MUX_ACLK_200_SEL << 12) \
+ | (MUX_ACLK_166_SEL << 8))
+
+/* CLK_SRC_TOP1 */
+#define MUX_ACLK_400_ISP_SEL 0x0
+#define MUX_ACLK_400_IOP_SEL 0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
+#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_ISP_SEL << 24) \
+ |(MUX_ACLK_400_IOP_SEL << 20) \
+ |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
+
+/* CLK_SRC_TOP2 */
+#define MUX_BPLL_USER_SEL 0x1
+#define MUX_MPLL_USER_SEL 0x1
+#define MUX_VPLL_SEL 0x0
+#define MUX_EPLL_SEL 0x0
+#define MUX_CPLL_SEL 0x0
+#define VPLLSRC_SEL 0x0
+#define CLK_SRC_TOP2_VAL ((MUX_BPLL_USER_SEL << 24) \
+ | (MUX_MPLL_USER_SEL << 20) \
+ | (MUX_VPLL_SEL << 16) \
+ | (MUX_EPLL_SEL << 12) \
+ | (MUX_CPLL_SEL << 8) \
+ | (VPLLSRC_SEL))
+/* CLK_SRC_TOP3 */
+#define MUX_ACLK_333_SUB_SEL 0x1
+#define MUX_ACLK_400_SUB_SEL 0x1
+#define MUX_ACLK_266_ISP_SUB_SEL 0x1
+#define MUX_ACLK_266_GPS_SUB_SEL 0x1
+#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
+#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
+ | (MUX_ACLK_400_SUB_SEL << 20) \
+ | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
+ | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
+ | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
+ | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
+ | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
+ | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+/* CLK_DIV_TOP0 */
+#define ACLK_300_RATIO 0x0
+#define ACLK_400_RATIO 0x3
+#define ACLK_333_RATIO 0x2
+#define ACLK_266_RATIO 0x2
+#define ACLK_200_RATIO 0x3
+#define ACLK_166_RATIO 0x5
+#define ACLK_133_RATIO 0x1
+#define ACLK_66_RATIO 0x5
+#define CLK_DIV_TOP0_VAL ((ACLK_300_RATIO << 28) \
+ | (ACLK_400_RATIO << 24) \
+ | (ACLK_333_RATIO << 20) \
+ | (ACLK_266_RATIO << 16) \
+ | (ACLK_200_RATIO << 12) \
+ | (ACLK_166_RATIO << 8) \
+ | (ACLK_133_RATIO << 4) \
+ | (ACLK_66_RATIO))
+
+/* CLK_DIV_TOP1 */
+#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
+#define ACLK_66_PRE_RATIO 0x1
+#define ACLK_400_ISP_RATIO 0x1
+#define ACLK_400_IOP_RATIO 0x1
+#define ACLK_300_GSCL_RATIO 0x0
+#define ACLK_266_GPS_RATIO 0x7
+
+#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
+ | (ACLK_66_PRE_RATIO << 24) \
+ | (ACLK_400_ISP_RATIO << 20) \
+ | (ACLK_400_IOP_RATIO << 16) \
+ | (ACLK_300_GSCL_RATIO << 12) \
+ | (ACLK_266_GPS_RATIO << 8))
+
+/* APLL_LOCK */
+#define APLL_LOCK_VAL (0x3E8)
+/* MPLL_LOCK */
+#define MPLL_LOCK_VAL (0x2F1)
+/* CPLL_LOCK */
+#define CPLL_LOCK_VAL (0x3E8)
+/* EPLL_LOCK */
+#define EPLL_LOCK_VAL (0x2321)
+/* VPLL_LOCK */
+#define VPLL_LOCK_VAL (0x2321)
+/* BPLL_LOCK */
+#define BPLL_LOCK_VAL (0x3E8)
+
+/* CLK_SRC_PERIC0 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define PWM_SEL 0
+#define UART4_SEL 6
+#define UART3_SEL 6
+#define UART2_SEL 6
+#define UART1_SEL 6
+#define UART0_SEL 6
+#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
+ | (UART4_SEL << 16) \
+ | (UART3_SEL << 12) \
+ | (UART2_SEL << 8) \
+ | (UART1_SEL << 4) \
+ | (UART0_SEL << 0))
+
+#define CLK_SRC_FSYS_VAL 0x66666
+#define CLK_DIV_FSYS0_VAL 0x0BB00000
+#define CLK_DIV_FSYS1_VAL 0x000f000f
+#define CLK_DIV_FSYS2_VAL 0x020f020f
+#define CLK_DIV_FSYS3_VAL 0x000f
+
+/* CLK_DIV_PERIC0 */
+#define UART5_RATIO 8
+#define UART4_RATIO 8
+#define UART3_RATIO 8
+#define UART2_RATIO 8
+#define UART1_RATIO 8
+#define UART0_RATIO 8
+#define CLK_DIV_PERIC0_VAL ((UART4_RATIO << 16) \
+ | (UART3_RATIO << 12) \
+ | (UART2_RATIO << 8) \
+ | (UART1_RATIO << 4) \
+ | (UART0_RATIO << 0))
+
+/* CLK_DIV_PERIC3 */
+#define PWM_RATIO 8
+#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL 0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL 0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL 0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL 0x10
+
+/* SCLK_SRC_ISP */
+#define SCLK_SRC_ISP_VAL 0x600
+/* CLK_DIV_ISP0 */
+#define CLK_DIV_ISP0_VAL 0x31
+
+/* CLK_DIV_ISP1 */
+#define CLK_DIV_ISP1_VAL 0x0
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL 0x1
+
+#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
+
+#define DISABLE 0
+#define ENABLE 1
+
+/*
+ * UART GPIO_A0/GPIO_A1 Control Register Value
+ * 0x2: UART Function
+ */
+#define EXYNOS5_GPIO_A0_CON_VAL 0x22222222
+#define EXYNOS5_GPIO_A1_CON_VAL 0x222222
+
+/* ULCON: UART Line Control Value 8N1 */
+#define WORD_LEN_5_BIT 0x00
+#define WORD_LEN_6_BIT 0x01
+#define WORD_LEN_7_BIT 0x02
+#define WORD_LEN_8_BIT 0x03
+
+#define STOP_BIT_1 0x00
+#define STOP_BIT_2 0x01
+
+#define NO_PARITY 0x00
+#define ODD_PARITY 0x4
+#define EVEN_PARITY 0x5
+#define FORCED_PARITY_CHECK_AS_1 0x6
+#define FORCED_PARITY_CHECK_AS_0 0x7
+
+#define INFRAMODE_NORMAL 0x00
+#define INFRAMODE_INFRARED 0x01
+
+#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \
+ | (NO_PARITY << 3) \
+ | (STOP_BIT_1 << 2) \
+ | (WORD_LEN_8_BIT << 0))
+
+/*
+ * UCON: UART Control Value
+ * Tx_interrupt Type: Level
+ * Rx_interrupt Type: Level
+ * Rx Timeout Enabled: Yes
+ * Rx-Error Atatus_Int Enable: Yes
+ * Loop_Back: No
+ * Break Signal: No
+ * Transmit mode : Interrupt request/polling
+ * Receive mode : Interrupt request/polling
+ */
+#define TX_PULSE_INTERRUPT 0
+#define TX_LEVEL_INTERRUPT 1
+#define RX_PULSE_INTERRUPT 0
+#define RX_LEVEL_INTERRUPT 1
+
+#define RX_TIME_OUT ENABLE
+#define RX_ERROR_STATE_INT_ENB ENABLE
+#define LOOP_BACK DISABLE
+#define BREAK_SIGNAL DISABLE
+
+#define TX_MODE_DISABLED 0X00
+#define TX_MODE_IRQ_OR_POLL 0X01
+#define TX_MODE_DMA 0X02
+
+#define RX_MODE_DISABLED 0X00
+#define RX_MODE_IRQ_OR_POLL 0X01
+#define RX_MODE_DMA 0X02
+
+#define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \
+ | (RX_LEVEL_INTERRUPT << 8) \
+ | (RX_TIME_OUT << 7) \
+ | (RX_ERROR_STATE_INT_ENB << 6) \
+ | (LOOP_BACK << 5) \
+ | (BREAK_SIGNAL << 4) \
+ | (TX_MODE_IRQ_OR_POLL << 2) \
+ | (RX_MODE_IRQ_OR_POLL << 0))
+
+/*
+ * UFCON: UART FIFO Control Value
+ * Tx FIFO Trigger LEVEL: 2 Bytes (001)
+ * Rx FIFO Trigger LEVEL: 2 Bytes (001)
+ * Tx Fifo Reset: No
+ * Rx Fifo Reset: No
+ * FIFO Enable: Yes
+ */
+#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00
+#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1
+#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2
+#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3
+#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4
+#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5
+#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6
+#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7
+
+#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0
+#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1
+#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2
+#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3
+#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4
+#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5
+#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6
+#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7
+
+#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES
+#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES
+#define TX_FIFO_RESET DISABLE
+#define RX_FIFO_RESET DISABLE
+#define FIFO_ENABLE ENABLE
+#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \
+ | (RX_FIFO_TRIGGER_LEVEL << 4) \
+ | (TX_FIFO_RESET << 2) \
+ | (RX_FIFO_RESET << 1) \
+ | (FIFO_ENABLE << 0))
+/*
+ * Baud Rate Division Value
+ * 115200 BAUD:
+ * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
+ * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
+ */
+#define UBRDIV_VAL 0x2F
+
+/*
+ * Fractional Part of Baud Rate Divisor:
+ * 115200 BAUD:
+ * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
+ * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
+ */
+#define UFRACVAL_VAL 0x3
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+#endif
diff --git a/boards.cfg b/boards.cfg
index 0b32532..3676e9d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -218,6 +218,7 @@ s5p_goni arm armv7 goni samsung
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
origen arm armv7 origen samsung exynos
s5pc210_universal arm armv7 universal_c210 samsung exynos
+smdk5250 arm armv7 smdk5250 samsung exynos
smdkv310 arm armv7 smdkv310 samsung exynos
harmony arm armv7 harmony nvidia tegra2
seaboard arm armv7 seaboard nvidia tegra2
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
new file mode 100644
index 0000000..9962c14
--- /dev/null
+++ b/include/configs/smdk5250.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
+#define CONFIG_S5P 1 /* S5P Family */
+#define CONFIG_EXYNOS5 1 /* which is in a Exynos5 Family */
+#define CONFIG_CPU_EXYNOS5250 1 /* which is in a Exynos5250 */
+#define CONFIG_SMDK5250 1 /* which is in a SMDK5250 */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_DCACHE_OFF 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* MACH_TYPE_ORIGEN macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5250 3774
+#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
+#define CONFIG_BAUDRATE 115200
+#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_S5P_MMC 1
+
+/* PWM */
+#define CONFIG_PWM 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "SMDK5250 # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ 1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
+
+#define CONFIG_NR_DRAM_BANKS 8
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH 1
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING " for SMDK5250"
+
+
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE (512)
+#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define MMC_MAX_CHANNEL 5
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+#endif /* __CONFIG_H */
--
1.7.5.4
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