[U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it.

[Christian Riesch]

On Thu, Jan 19, 2012 at 12:54 PM, Aneesh V <aneesh at ti.com> wrote:
> On Thursday 19 January 2012 05:00 PM, Christian Riesch wrote:
>> On Thu, Jan 19, 2012 at 11:17 AM, Aneesh V<aneesh at ti.com>  wrote:
>>> On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
>>>>   Tried a few things on my end.
>>>>   * Read the D-cache value in the spl, and confirmed that the data
>>>>     cache is indeed not enabled.
>>>
>>> What is the value of the B bit in CP15 SCR register? I wonder if RBL is
>>> doing all the IMB operations required after copying the SPL image and
>>> before executing it. IMB is required for consistency between data and
>>> instruction sides.
>>
>> Only if caches are used, right? Or also without caches?
>> Tom wrote that RBL does not turn on cache.
>> Regards, Christian
>
> Only D-cache seems to be disabled in this case. I-cache and Write
> buffer are likely to be enabled. If so, all the IMB operations except
> the data-cache flushing are still relevant.

Tom, when you wrote that RBL does not turn on caches, did you mean it
never turns it on or it turns some of them on and turns them off
before exit?
Christian