[U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it.

[James W.]

so sorry to you,
i think it's difference between DISABLE and Flush.

be careful.


On Wed, Jan 11, 2012 at 2:12 AM, Sughosh Ganu <urwithsughosh at gmail.com>wrote:

> The current implementation invalidates the cache instead of flushing
> it. This causes problems on platforms where the spl/u-boot is already
> loaded to the RAM, with caches enabled by a first stage bootloader.
>
> The V bit of the cp15's control register c1 is set to the value of
> VINITHI on reset. Do not clear this bit by default, as there are SOC's
> with no valid memory region at 0x0.
>
> Signed-off-by: Sughosh Ganu <urwithsughosh at gmail.com>
> Cc: Albert Aribaud <albert.u.boot at aribaud.net>
> ---
>
> Changes since V1
> * Added arm926 keyword to the subject line
> * Removed the superfluous setting of r0.
> * Fixed the comment to reflect the fact that V is not being cleared
>
>  arch/arm/cpu/arm926ejs/start.S |    9 ++++++---
>  1 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/start.S
> b/arch/arm/cpu/arm926ejs/start.S
> index 6a09c02..6e261c2 100644
> --- a/arch/arm/cpu/arm926ejs/start.S
> +++ b/arch/arm/cpu/arm926ejs/start.S
> @@ -355,17 +355,20 @@ _dynsym_start_ofs:
>  */
>  cpu_init_crit:
>        /*
> -        * flush v4 I/D caches
> +        * flush D cache before disabling it
>         */
>        mov     r0, #0
> -       mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
> +flush_dcache:
> +       mrc     p15, 0, r15, c7, c10, 3
> +       bne     flush_dcache
> +
>        mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
>
>        /*
>         * disable MMU stuff and caches
>         */
>        mrc     p15, 0, r0, c1, c0, 0
> -       bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS)
> */
> +       bic     r0, r0, #0x00000300     /* clear bits 9:8 ( --RS) */
>        bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
>        orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
>        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
> --
> 1.7.5.4
>
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