[U-Boot] mx28 spl power cpu clock configuration

[Marek Vasut]

> Hi Robert,
> 
> On 1/25/12, Marek Vasut <marek.vasut at gmail.com> wrote:
> >> Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock
> >> gating - before disabling PLL bypass?
> > 
> > This seems reasonable. Fabio, can you comment?
> 
> Could you please post a patch with your proposed change so that we can test
> it?
> 

Hi Fabio,

I bought a really crappy custom board a few days ago (some china-made crap) 
sporting mx287, but apparently I'm hitting similar issue you do here.

When I swap power_init and mem_init though, the board boots fine, othervise it 
hangs.

M