[U-Boot] [PATCH V4 1/7] mxc_spi: move machine specifics into CPU headers

Eric Nelson eric.nelson at boundarydevices.com
Sun Jan 29 21:01:13 CET 2012 

On 01/29/2012 12:16 PM, Marek Vasut wrote:
>> Move (E)CSPI register declarations into the imx-regs.h files for each
>> supported CPU
>>
>> Introduce two new macros to control conditional setup
>>       MXC_CSPI - Used for processors with the Configurable Serial Peripheral
>> Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable...
>> (MX5x, MX6x)
>>
>> Signed-off-by: Eric Nelson<eric.nelson at boundarydevices.com>
>> Acked-by: Dirk Behme<dirk.behme at de.bosch.com>
>> Acked-by: Stefano Babic<sbabic at denx.de>
>> ---
>>   arch/arm/include/asm/arch-mx31/imx-regs.h |   27 ++++++++
>>   arch/arm/include/asm/arch-mx35/imx-regs.h |   25 ++++++++
>>   arch/arm/include/asm/arch-mx5/imx-regs.h  |   30 +++++++++
>>   drivers/spi/mxc_spi.c                     |   93
>> ++--------------------------- 4 files changed, 88 insertions(+), 87
>> deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h
>> b/arch/arm/include/asm/arch-mx31/imx-regs.h index 6a517dd..70e3338 100644
>> --- a/arch/arm/include/asm/arch-mx31/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
>> @@ -890,4 +890,31 @@ struct esdc_regs {
>>   #define MXC_EHCI_IPPUE_DOWN		(1<<  8)
>>   #define MXC_EHCI_IPPUE_UP		(1<<  9)
>>
>> +/*
>> + * CSPI register definitions
>> + */
>> +#define MXC_CSPI
>> +#define MXC_CSPICTRL_EN		(1<<  0)
>> +#define MXC_CSPICTRL_MODE	(1<<  1)
>> +#define MXC_CSPICTRL_XCH	(1<<  2)
>> +#define MXC_CSPICTRL_SMC	(1<<  3)
>> +#define MXC_CSPICTRL_POL	(1<<  4)
>> +#define MXC_CSPICTRL_PHA	(1<<  5)
>> +#define MXC_CSPICTRL_SSCTL	(1<<  6)
>> +#define MXC_CSPICTRL_SSPOL	(1<<  7)
>> +#define MXC_CSPICTRL_CHIPSELECT(x)	(((x)&  0x3)<<  24)
>> +#define MXC_CSPICTRL_BITCOUNT(x)	(((x)&  0x1f)<<  8)
>> +#define MXC_CSPICTRL_DATARATE(x)	(((x)&  0x7)<<  16)
>> +#define MXC_CSPICTRL_TC		(1<<  8)
>> +#define MXC_CSPICTRL_RXOVF	(1<<  6)
>> +#define MXC_CSPICTRL_MAXBITS	0x1f
>> +
>> +#define MXC_CSPIPERIOD_32KHZ	(1<<  15)
>> +#define MAX_SPI_BYTES	4
>> +
>> +#define MXC_SPI_BASE_ADDRESSES \
>> +	0x43fa4000, \
>> +	0x50010000, \
>> +	0x53f84000,
>> +
>>   #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
>> diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h
>> b/arch/arm/include/asm/arch-mx35/imx-regs.h index df74508..e570ad1 100644
>> --- a/arch/arm/include/asm/arch-mx35/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
>> @@ -179,6 +179,31 @@
>>   #define IPU_CONF_IC_EN		(1<<1)
>>   #define IPU_CONF_SCI_EN		(1<<0)
>>
>> +/*
>> + * CSPI register definitions
>> + */
>> +#define MXC_CSPI
>> +#define MXC_CSPICTRL_EN		(1<<  0)
>> +#define MXC_CSPICTRL_MODE	(1<<  1)
>> +#define MXC_CSPICTRL_XCH	(1<<  2)
>> +#define MXC_CSPICTRL_SMC	(1<<  3)
>> +#define MXC_CSPICTRL_POL	(1<<  4)
>> +#define MXC_CSPICTRL_PHA	(1<<  5)
>> +#define MXC_CSPICTRL_SSCTL	(1<<  6)
>> +#define MXC_CSPICTRL_SSPOL	(1<<  7)
>> +#define MXC_CSPICTRL_CHIPSELECT(x)	(((x)&  0x3)<<  12)
>> +#define MXC_CSPICTRL_BITCOUNT(x)	(((x)&  0xfff)<<  20)
>> +#define MXC_CSPICTRL_DATARATE(x)	(((x)&  0x7)<<  16)
>> +#define MXC_CSPICTRL_TC		(1<<  7)
>> +#define MXC_CSPICTRL_RXOVF	(1<<  6)
>> +#define MXC_CSPICTRL_MAXBITS	0xfff
>> +#define MXC_CSPIPERIOD_32KHZ	(1<<  15)
>> +#define MAX_SPI_BYTES	4
>> +
>> +#define MXC_SPI_BASE_ADDRESSES \
>> +	0x43fa4000, \
>> +	0x50010000,
>> +
>>   #define GPIO_PORT_NUM		3
>>   #define GPIO_NUM_PIN		32
>>
>> diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h
>> b/arch/arm/include/asm/arch-mx5/imx-regs.h index 0ee88d2..4fa6658 100644
>> --- a/arch/arm/include/asm/arch-mx5/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
>> @@ -223,6 +223,36 @@
>>   #define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
>>
>>   /*
>> + * CSPI register definitions
>> + */
>> +#define MXC_ECSPI
>> +#define MXC_CSPICTRL_EN		(1<<  0)
>> +#define MXC_CSPICTRL_MODE	(1<<  1)
>> +#define MXC_CSPICTRL_XCH	(1<<  2)
>> +#define MXC_CSPICTRL_CHIPSELECT(x)	(((x)&  0x3)<<  12)
>> +#define MXC_CSPICTRL_BITCOUNT(x)	(((x)&  0xfff)<<  20)
>> +#define MXC_CSPICTRL_PREDIV(x)	(((x)&  0xF)<<  12)
>> +#define MXC_CSPICTRL_POSTDIV(x)	(((x)&  0xF)<<  8)
>> +#define MXC_CSPICTRL_SELCHAN(x)	(((x)&  0x3)<<  18)
>> +#define MXC_CSPICTRL_MAXBITS	0xfff
>> +#define MXC_CSPICTRL_TC		(1<<  7)
>> +#define MXC_CSPICTRL_RXOVF	(1<<  6)
>> +#define MXC_CSPIPERIOD_32KHZ	(1<<  15)
>> +#define MAX_SPI_BYTES	32
>> +
>> +/* Bit position inside CTRL register to be associated with SS */
>> +#define MXC_CSPICTRL_CHAN	18
>> +
>> +/* Bit position inside CON register to be associated with SS */
>> +#define MXC_CSPICON_POL		4
>> +#define MXC_CSPICON_PHA		0
>> +#define MXC_CSPICON_SSPOL	12
>> +#define MXC_SPI_BASE_ADDRESSES \
>> +	CSPI1_BASE_ADDR, \
>> +	CSPI2_BASE_ADDR, \
>> +	CSPI3_BASE_ADDR,
>> +
>> +/*
>>    * Number of GPIO pins per port
>>    */
>>   #define GPIO_NUM_PIN            32
>> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
>> index 2fa7486..2e15318 100644
>> --- a/drivers/spi/mxc_spi.c
>> +++ b/drivers/spi/mxc_spi.c
>> @@ -33,93 +33,12 @@
>>
>>   #error "i.MX27 CSPI not supported due to drastic differences in register
>> definitions" \ "See linux mxc_spi driver from Freescale for details."
>> -
>> -#elif defined(CONFIG_MX31)
>> -
>> -#define MXC_CSPICTRL_EN		(1<<  0)
>> -#define MXC_CSPICTRL_MODE	(1<<  1)
>> -#define MXC_CSPICTRL_XCH	(1<<  2)
>> -#define MXC_CSPICTRL_SMC	(1<<  3)
>> -#define MXC_CSPICTRL_POL	(1<<  4)
>> -#define MXC_CSPICTRL_PHA	(1<<  5)
>> -#define MXC_CSPICTRL_SSCTL	(1<<  6)
>> -#define MXC_CSPICTRL_SSPOL	(1<<  7)
>> -#define MXC_CSPICTRL_CHIPSELECT(x)	(((x)&  0x3)<<  24)
>> -#define MXC_CSPICTRL_BITCOUNT(x)	(((x)&  0x1f)<<  8)
>> -#define MXC_CSPICTRL_DATARATE(x)	(((x)&  0x7)<<  16)
>> -#define MXC_CSPICTRL_TC		(1<<  8)
>> -#define MXC_CSPICTRL_RXOVF	(1<<  6)
>> -#define MXC_CSPICTRL_MAXBITS	0x1f
>> -
>> -#define MXC_CSPIPERIOD_32KHZ	(1<<  15)
>> -#define MAX_SPI_BYTES	4
>> -
>> -static unsigned long spi_bases[] = {
>> -	0x43fa4000,
>> -	0x50010000,
>> -	0x53f84000,
>> -};
>> -
>> -#elif defined(CONFIG_MX51)
>> -
>> -#define MXC_CSPICTRL_EN		(1<<  0)
>> -#define MXC_CSPICTRL_MODE	(1<<  1)
>> -#define MXC_CSPICTRL_XCH	(1<<  2)
>> -#define MXC_CSPICTRL_CHIPSELECT(x)	(((x)&  0x3)<<  12)
>> -#define MXC_CSPICTRL_BITCOUNT(x)	(((x)&  0xfff)<<  20)
>> -#define MXC_CSPICTRL_PREDIV(x)	(((x)&  0xF)<<  12)
>> -#define MXC_CSPICTRL_POSTDIV(x)	(((x)&  0xF)<<  8)
>> -#define MXC_CSPICTRL_SELCHAN(x)	(((x)&  0x3)<<  18)
>> -#define MXC_CSPICTRL_MAXBITS	0xfff
>> -#define MXC_CSPICTRL_TC		(1<<  7)
>> -#define MXC_CSPICTRL_RXOVF	(1<<  6)
>> -
>> -#define MXC_CSPIPERIOD_32KHZ	(1<<  15)
>> -#define MAX_SPI_BYTES	32
>> -
>> -/* Bit position inside CTRL register to be associated with SS */
>> -#define MXC_CSPICTRL_CHAN	18
>> -
>> -/* Bit position inside CON register to be associated with SS */
>> -#define MXC_CSPICON_POL		4
>> -#define MXC_CSPICON_PHA		0
>> -#define MXC_CSPICON_SSPOL	12
>> -
>> -static unsigned long spi_bases[] = {
>> -	CSPI1_BASE_ADDR,
>> -	CSPI2_BASE_ADDR,
>> -	CSPI3_BASE_ADDR,
>> -};
>> -
>> -#elif defined(CONFIG_MX35)
>> -
>> -#define MXC_CSPICTRL_EN		(1<<  0)
>> -#define MXC_CSPICTRL_MODE	(1<<  1)
>> -#define MXC_CSPICTRL_XCH	(1<<  2)
>> -#define MXC_CSPICTRL_SMC	(1<<  3)
>> -#define MXC_CSPICTRL_POL	(1<<  4)
>> -#define MXC_CSPICTRL_PHA	(1<<  5)
>> -#define MXC_CSPICTRL_SSCTL	(1<<  6)
>> -#define MXC_CSPICTRL_SSPOL	(1<<  7)
>> -#define MXC_CSPICTRL_CHIPSELECT(x)	(((x)&  0x3)<<  12)
>> -#define MXC_CSPICTRL_BITCOUNT(x)	(((x)&  0xfff)<<  20)
>> -#define MXC_CSPICTRL_DATARATE(x)	(((x)&  0x7)<<  16)
>> -#define MXC_CSPICTRL_TC		(1<<  7)
>> -#define MXC_CSPICTRL_RXOVF	(1<<  6)
>> -#define MXC_CSPICTRL_MAXBITS	0xfff
>> -
>> -#define MXC_CSPIPERIOD_32KHZ	(1<<  15)
>> -#define MAX_SPI_BYTES	4
>> +#endif
>>
>>   static unsigned long spi_bases[] = {
>> -	0x43fa4000,
>> -	0x50010000,
>> +	MXC_SPI_BASE_ADDRESSES
>>   };
>>
>> -#else
>> -#error "Unsupported architecture"
>> -#endif
>> -
>>   #define OUT	MXC_GPIO_DIRECTION_OUT
>>
>>   #define reg_read readl
>> @@ -129,7 +48,7 @@ struct mxc_spi_slave {
>>   	struct spi_slave slave;
>>   	unsigned long	base;
>>   	u32		ctrl_reg;
>> -#if defined(CONFIG_MX51)
>> +#if defined(MXC_ECSPI)
>>   	u32		cfg_reg;
>>   #endif
>>   	int		gpio;
>> @@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div)
>>   	return i;
>>   }
>>
>> -#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
>> +#ifdef MXC_CSPI
>>   static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
>>   		unsigned int max_hz, unsigned int mode)
>>   {
>> @@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs,
>> unsigned int cs, }
>>   #endif
>>
>> -#if defined(CONFIG_MX51)
>> +#ifdef MXC_ECSPI
>>   static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
>>   		unsigned int max_hz, unsigned int mode)
>>   {
>> @@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned
>> int bitlen, MXC_CSPICTRL_BITCOUNT(bitlen - 1);
>>
>>   	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
>> -#ifdef CONFIG_MX51
>> +#ifdef MXC_ECSPI
>
> Good, but what about the boards that use these? Won't they be broken?
>
No. If you look above, you'll see that MXC_ECSPI is unconditionally
defined in arch/arm/include/asm/arch-mx5/imx-regs.h.

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