[U-Boot] [PATCH v5 4/7] arm, arm926ejs: Do not clear the V bit on DA850 SoCs

[Sughosh Ganu]

hi Christian,

On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch <
christian.riesch at omicron.at> wrote:

> The V bit of the c1 register of CP15 should not be cleared
> since the SoC has no valid memory at 0x00000000.
>
> Signed-off-by: Christian Riesch <christian.riesch at omicron.at>
> Reported-by: Sughosh Ganu <urwithsughosh at gmail.com>
> Cc: Albert Aribaud <albert.u.boot at aribaud.net>
> Cc: Tom Rini <trini at ti.com>
> ---
>  arch/arm/cpu/arm926ejs/start.S |    5 ++++-
>  1 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/start.S
> b/arch/arm/cpu/arm926ejs/start.S
> index b39ed8a..b350480 100644
> --- a/arch/arm/cpu/arm926ejs/start.S
> +++ b/arch/arm/cpu/arm926ejs/start.S
> @@ -372,7 +372,10 @@ flush_dcache:
>         * disable MMU and D cache, and enable I cache
>         */
>        mrc     p15, 0, r0, c1, c0, 0
> -       bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS)
> */
> +       bic     r0, r0, #0x00000300     /* clear bits 9:8 (---- --RS) */
> +#ifndef CONFIG_SOC_DA850
> +       bic     r0, r0, #0x00002000     /* clear bit 13 (--V- ----) */
> +#endif
>

Instead of checking for a particular SOC, can we introduce a generic
config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other
SOC's have a similar requirement, it won't be needed to keep adding checks
here. It would also help in case this needs to be implemented for other arm
cores, so that we can have a common config option for bypassing this V-bit
clear. Just my suggestion. Maybe Tom and Albert can comment.

I will test your patch series on my hawkboard and let you know the results
tomorrow. Thanks for clubbing it all together.

-sughosh