[U-Boot] [PATCH 12/13] S3C6400: clear memory init variable
Zhong Hongbo
bocui107 at gmail.com
Sat Jul 7 11:57:11 CEST 2012
From: Zhong Hongbo <bocui107 at gmail.com>
Signed-off-by: Zhong Hongbo <bocui107 at gmail.com>
---
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 173 +--------------------------
board/samsung/smdk6400/mem_init.S | 110 +++++++++---------
2 files changed, 56 insertions(+), 227 deletions(-)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 736cea2..b254282 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -41,124 +41,16 @@
#include <asm/hardware.h>
#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-
-/*
- * GPIO
- */
#define ELFIN_GPIO_BASE 0x7f008000
-
-/*
- * Bus Matrix
- */
-#define ELFIN_MEM_SYS_CFG 0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
-
-/*
- * Memory controller
- */
#define ELFIN_SROM_BASE 0x70000000
-
-/*
- * SDRAM Controller
- */
#define ELFIN_DMC0_BASE 0x7e000000
#define ELFIN_DMC1_BASE 0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS 0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD 0x08
-#define INDEX_DMC_MEMORY_CFG 0x0C
-#define INDEX_DMC_REFRESH_PRD 0x10
-#define INDEX_DMC_CAS_LATENCY 0x14
-#define INDEX_DMC_T_DQSS 0x18
-#define INDEX_DMC_T_MRD 0x1C
-#define INDEX_DMC_T_RAS 0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD 0x28
-#define INDEX_DMC_T_RFC 0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD 0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR 0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR 0x44
-#define INDEX_DMC_T_ESR 0x48
-#define INDEX_DMC_MEMORY_CFG2 0x4C
-#define INDEX_DMC_CHIP_0_CFG 0x200
-#define INDEX_DMC_CHIP_1_CFG 0x204
-#define INDEX_DMC_CHIP_2_CFG 0x208
-#define INDEX_DMC_CHIP_3_CFG 0x20C
-#define INDEX_DMC_USER_STATUS 0x300
-#define INDEX_DMC_USER_CONFIG 0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0 0x0c0000
-#define DMC_NOP1 0x1c0000
-#define DMC_PA0 0x000000 /* Precharge all */
-#define DMC_PA1 0x100000
-#define DMC_AR0 0x040000 /* Autorefresh */
-#define DMC_AR1 0x140000
-#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
-#define DMC_SDR_MR1 0x180032
-#define DMC_DDR_MR0 0x080162
-#define DMC_DDR_MR1 0x180162
-#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
-#define DMC_mDDR_MR1 0x180032
-#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
-#define DMC_mSDR_EMR1 0x1a0000
-#define DMC_DDR_EMR0 0x090000
-#define DMC_DDR_EMR1 0x190000
-#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
-#define DMC_mDDR_EMR1 0x1a0000
-
-/*
- * Definitions for memory configuration
- * Set memory configuration
- * active_chips = 1'b0 (1 chip)
- * qos_master_chip = 3'b000(ARID[3:0])
- * memory burst = 3'b010(burst 4)
- * stop_mem_clock = 1'b0(disable dynamical stop)
- * auto_power_down = 1'b0(disable auto power-down mode)
- * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
- * ap_bit = 1'b0 (bit position of auto-precharge is 10)
- * row_bits = 3'b010(# row address 13)
- * column_bits = 3'b010(# column address 10 )
- *
- * Set user configuration
- * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
- *
- * Set chip select for chip [n]
- * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
- * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
- */
-
-/*
- * Nand flash controller
- */
+#define ELFIN_MEM_SYS_CFG 0x7e00f120
#define ELFIN_NAND_BASE 0x70200000
-
-/*
- * Interrupt
- */
#define ELFIN_VIC0_BASE_ADDR 0x71200000
#define ELFIN_VIC1_BASE_ADDR 0x71300000
-
-/*
- * Watchdog timer
- */
#define ELFIN_WATCHDOG_BASE 0x7E004000
-
-/*
- * UART
- */
#define ELFIN_UART_BASE 0x7F005000
-
-/*
- * PWM timer
- */
#define ELFIN_TIMER_BASE 0x7F006000
#define STARTUP_AMDIV 533
@@ -187,69 +79,6 @@
(STARTUP_HCLKDIV + 1))
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */
-#define DMC1_MEM_CFG2 0xB45
-#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */
-#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH 7800 /* ns */
-#define DDR_tRAS 45 /* ns (min: 45ns)*/
-#define DDR_tRC 68 /* ns (min: 67.5ns)*/
-#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
-#define DDR_tRFC 80 /* ns (min: 80ns)*/
-#define DDR_tRP 23 /* ns (min: 22.5ns)*/
-#define DDR_tRRD 15 /* ns (min: 15ns)*/
-#define DDR_tWR 15 /* ns (min: 15ns)*/
-#define DDR_tXSR 120 /* ns (min: 120ns)*/
-#define DDR_CASL 3 /* CAS Latency 3 */
-
-/*
- * mDDR memory configuration
- */
-
-#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
-
-#define DMC_DDR_BA_EMRS 2
-#define DMC_DDR_MEM_CASLAT 3
-/* 6 Set Cas Latency to 3 */
-#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
-/* Min 0.75 ~ 1.25 */
-#define DMC_DDR_t_DQSS 1
-/* Min 2 tck */
-#define DMC_DDR_t_MRD 2
-/* 7, Min 45ns */
-#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
-/* 10, Min 67.5ns */
-#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
-/* 4,5(TRM), Min 22.5ns */
-#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
-#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
-/* 11,18(TRM) Min 80ns */
-#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
-#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
-/* 4, 5(TRM) Min 22.5ns */
-#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
-#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
-/* 3, Min 15ns */
-#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
-/* Min 15ns */
-#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
-#define DMC_DDR_t_WTR 2
-/* 1tck + tIS(1.5ns) */
-#define DMC_DDR_t_XP 2
-/* 17, Min 120ns */
-#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
-#define DMC_DDR_t_ESR DMC_DDR_t_XSR
-/* TRM 2656 */
-#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
-/* 2b01 : mDDR */
-#define DMC_DDR_USER_CONFIG 1
-
#ifndef __ASSEMBLY__
static inline unsigned int s3c64xx_get_base_uart(void)
{
diff --git a/board/samsung/smdk6400/mem_init.S b/board/samsung/smdk6400/mem_init.S
index 4a012e5..8b41484 100644
--- a/board/samsung/smdk6400/mem_init.S
+++ b/board/samsung/smdk6400/mem_init.S
@@ -36,98 +36,98 @@ mem_ctrl_asm_init:
ldr r0, =ELFIN_DMC1_BASE
ldr r1, =0x4
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
+ str r1, [r0, #0x04] @ INDEX_DMC_MEMC_CMD
- ldr r1, =DMC_DDR_REFRESH_PRD
- str r1, [r0, #INDEX_DMC_REFRESH_PRD]
+ ldr r1, =0x40d
+ str r1, [r0, #0x10] @ INDEX_DMC_REFRESH_PRD
- ldr r1, =DMC_DDR_CAS_LATENCY
- str r1, [r0, #INDEX_DMC_CAS_LATENCY]
+ ldr r1, =(0x3 << 1)
+ str r1, [r0, #0x14] @ INDEX_DMC_CAS_LATENCY
- ldr r1, =DMC_DDR_t_DQSS
- str r1, [r0, #INDEX_DMC_T_DQSS]
+ ldr r1, =0x1
+ str r1, [r0, #0x18] @ INDEX_DMC_T_DQSS
- ldr r1, =DMC_DDR_t_MRD
- str r1, [r0, #INDEX_DMC_T_MRD]
+ ldr r1, =0x2
+ str r1, [r0, #0x1c] @ INDEX_DMC_T_MRD
- ldr r1, =DMC_DDR_t_RAS
- str r1, [r0, #INDEX_DMC_T_RAS]
+ ldr r1, =0x6
+ str r1, [r0, #0x20] @ INDEX_DMC_T_RAS
- ldr r1, =DMC_DDR_t_RC
- str r1, [r0, #INDEX_DMC_T_RC]
+ ldr r1, =0xa
+ str r1, [r0, #0x24] @ INDEX_DMC_T_RC
- ldr r1, =DMC_DDR_t_RCD
- ldr r2, =DMC_DDR_schedule_RCD
+ ldr r1, =0x4
+ ldr r2, =(0x1 << 3)
orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RCD]
+ str r1, [r0, #0x28] @ INDEX_DMC_T_RCD
- ldr r1, =DMC_DDR_t_RFC
- ldr r2, =DMC_DDR_schedule_RFC
+ ldr r1, =0xb
+ ldr r2, =(0x8 << 5)
orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RFC]
+ str r1, [r0, #0x2c] @ INDEX_DMC_T_RFC
- ldr r1, =DMC_DDR_t_RP
- ldr r2, =DMC_DDR_schedule_RP
+ ldr r1, =0x4
+ ldr r2, =(0x1 << 3)
orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RP]
+ str r1, [r0, #0x30] @ INDEX_DMC_T_RP
- ldr r1, =DMC_DDR_t_RRD
- str r1, [r0, #INDEX_DMC_T_RRD]
+ ldr r1, =0x2
+ str r1, [r0, #0x34] @ INDEX_DMC_T_RRD
- ldr r1, =DMC_DDR_t_WR
- str r1, [r0, #INDEX_DMC_T_WR]
+ ldr r1, =0x2
+ str r1, [r0, #0x38] @ INDEX_DMC_T_WR
- ldr r1, =DMC_DDR_t_WTR
- str r1, [r0, #INDEX_DMC_T_WTR]
+ ldr r1, =0x2
+ str r1, [r0, #0x3c] @ INDEX_DMC_T_WTR
- ldr r1, =DMC_DDR_t_XP
- str r1, [r0, #INDEX_DMC_T_XP]
+ ldr r1, =0x2
+ str r1, [r0, #0x40] @ INDEX_DMC_T_XP
- ldr r1, =DMC_DDR_t_XSR
- str r1, [r0, #INDEX_DMC_T_XSR]
+ ldr r1, =0x10
+ str r1, [r0, #0x44] @ INDEX_DMC_T_XSR
- ldr r1, =DMC_DDR_t_ESR
- str r1, [r0, #INDEX_DMC_T_ESR]
+ ldr r1, =0x10
+ str r1, [r0, #0x48] @ INDEX_DMC_T_ESR
- ldr r1, =DMC1_MEM_CFG
- str r1, [r0, #INDEX_DMC_MEMORY_CFG]
+ ldr r1, =0x00010012
+ str r1, [r0, #0x0c] @ INDEX_DMC_MEMORY_CFG
- ldr r1, =DMC1_MEM_CFG2
- str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
+ ldr r1, =0x000100122
+ str r1, [r0, #0x4c] @ INDEX_DMC_MEMORY_CFG2
- ldr r1, =DMC1_CHIP0_CFG
- str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
+ ldr r1, =0x150F8
+ str r1, [r0, #0x200] @ INDEX_DMC_CHIP_0_CFG
- ldr r1, =DMC_DDR_32_CFG
- str r1, [r0, #INDEX_DMC_USER_CONFIG]
+ ldr r1, =0x0
+ str r1, [r0, #0x304] @ INDEX_DMC_USER_CONFIG
/* DMC0 DDR Chip 0 configuration direct command reg */
- ldr r1, =DMC_NOP0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x0c0000
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
/* Precharge All */
- ldr r1, =DMC_PA0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x000000
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
/* Auto Refresh 2 time */
- ldr r1, =DMC_AR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x040000
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
+ str r1, [r0, #0x08]
/* MRS */
- ldr r1, =DMC_mDDR_EMR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x0a0000
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
/* Mode Reg */
- ldr r1, =DMC_mDDR_MR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x080032
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
/* Enable DMC1 */
mov r1, #0x0
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
+ str r1, [r0, #0x04] @ INDEX_DMC_MEMC_CMD
check_dmc1_ready:
- ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
+ ldr r1, [r0, #0x00] @ INDEX_DMC_MEMC_STATUS
mov r2, #0x3
and r1, r1, r2
cmp r1, #0x1
--
1.7.5.4
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