[U-Boot] [PATCH] nds32: split common cache access from cpu into lib

[Marek Vasut]

Dear Macpaul Lin,

> This commit does the following updates.
> 1. Split the common cache access from cpu.c into lib folder.
> 2. Rename the following cache api to adapt common.h
>  - dcache_flush_rang -> flush_dcache_rang
>  - icache_inval_range -> invalidate_icache_range
> 3. Add invalidate_dcache_range

So basically this connects it to standard cache api?

[...]
> diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c
[...]
> +static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
> +{
> +	if (cache == ICACHE)
> +		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
> +					>> ICM_CFG_OFF_ISZ) - 1);


These crazy macros can be probably done easier and can share some code maybe? 
Maybe not though, I dunno, just a thought.

> +	else
> +		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
> +					>> DCM_CFG_OFF_DSZ) - 1);
> +}
> +
> +void flush_dcache_range(unsigned long start, unsigned long end)
> +{
> +	unsigned long line_size;
> +
> +	line_size = CACHE_LINE_SIZE(DCACHE);
> +
> +	while (end > start) {
> +		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
> +		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));

You probably want to do those two calls in one asm volatile () block. And this 
too ... use "asm volatile()" and not "__asm__ volatile" or "asm __volatile__" 
and similar combinations of these, just a nit ;-)

> +		start += line_size;
> +	}
> +}
> +
> +void invalidate_icache_range(unsigned long start, unsigned long end)
> +{
> +	unsigned long line_size;
> +
> +	line_size = CACHE_LINE_SIZE(ICACHE);
> +	while (end > start) {
> +		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
> +		start += line_size;
> +	}
> +}
> +
> +void invalidate_dcache_range(unsigned long start, unsigned long end)
> +{
> +	unsigned long line_size;
> +
> +	line_size = CACHE_LINE_SIZE(DCACHE);
> +	while (end > start) {
> +		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
> +		start += line_size;
> +	}
> +}
> +
> +void flush_cache(unsigned long addr, unsigned long size)
> +{
> +	flush_dcache_range(addr, addr + size);
> +	invalidate_icache_range(addr, addr + size);

You probably want to flush dcache in here and that's it.

> +}
> +
> +void icache_enable(void)
> +{
> +	__asm__ __volatile__ (

See my nit above for the rest ;-) But all in all it's good, we should be 
applying this around V2-V3 of this patch, for the -next release. Thanks for your 
patch!