[U-Boot] [PATCH u-boot-arm/next v2 1/1] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Enric Balletbò i Serra]

2012/7/19 Javier Martinez Canillas <javier at dowhile0.org>:
> On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni
> <thomas.petazzoni at free-electrons.com> wrote:
>> Le Tue, 17 Jul 2012 02:15:17 +0200,
>> Javier Martinez Canillas <javier at dowhile0.org> a écrit :
>>
>>> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
>>> +             u32 *mr)
>>> +{
>>> +     *mr = MICRON_V_MR_165;
>>> +#ifdef CONFIG_BOOT_NAND
>>> +     *mcfg = MICRON_V_MCFG_165(512 << 20);
>>> +     *ctrla = MICRON_V_ACTIMA_165;
>>> +     *ctrlb = MICRON_V_ACTIMB_165;
>>> +     *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>>
>> I thought the NAND version of the IGEPv2 was capable of using the 200
>> Mhz timings. At least, from the limited testing I had done, it seemed
>> to work.
>>
>> Best regards,
>>
>> Thomas
>> --
>
> Hi Thomas,
>
> Yes, you are right. I just tested the following patch on my NAND
> version IGEPv2 and it seems to work just fine.
>
> Do you know if the OneNAND version also supports 200 MHz timings? If I
> remember correctly the OMAP3730 version did but the OMAP3530 didn't.
>
> I guess Enric knows the answer :-)
>
> I can re-send a v2 with these modifications or send an incremental
> patch once this get merged, whatever you guys think is better.
>
> Thomas, Enric and Tom,
>
> Sorry if you got this mail twice but my first mail got bounced from
> the list since I sent from a another non-registered account, so I'm
> resending to the list again.
>
> Best regards,
> Javier
>
> diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
> index 40436d6..9035af7 100644
> --- a/board/isee/igep0020/igep0020.c
> +++ b/board/isee/igep0020/igep0020.c
> @@ -77,10 +77,10 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
> u32 *ctrlb, u32 *rfr_ctrl,
>  {
>         *mr = MICRON_V_MR_165;
>  #ifdef CONFIG_BOOT_NAND
> -       *mcfg = MICRON_V_MCFG_165(512 << 20);
> -       *ctrla = MICRON_V_ACTIMA_165;
> -       *ctrlb = MICRON_V_ACTIMB_165;
> -       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +       *mcfg = MICRON_V_MCFG_200(512 << 20);
> +       *ctrla = MICRON_V_ACTIMA_200;
> +       *ctrlb = MICRON_V_ACTIMB_200;
> +       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>  #else
>         *mcfg = NUMONYX_V_MCFG_165(512 << 20);
>         *ctrla = NUMONYX_V_ACTIMA_165;
> diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
> index 41a7548..5c87f2d 100644
> --- a/board/isee/igep0030/igep0030.c
> +++ b/board/isee/igep0030/igep0030.c
> @@ -64,10 +64,10 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
> u32 *ctrlb, u32 *rfr_ctrl,
>  {
>         *mr = MICRON_V_MR_165;
>  #ifdef CONFIG_BOOT_NAND
> -       *mcfg = MICRON_V_MCFG_165(512 << 20);
> -       *ctrla = MICRON_V_ACTIMA_165;
> -       *ctrlb = MICRON_V_ACTIMB_165;
> -       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +       *mcfg = MICRON_V_MCFG_200(512 << 20);
> +       *ctrla = MICRON_V_ACTIMA_200;
> +       *ctrlb = MICRON_V_ACTIMB_200;
> +       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>  #else
>         *mcfg = NUMONYX_V_MCFG_165(512 << 20);
>         *ctrla = NUMONYX_V_ACTIMA_165;
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Both memories can work at 200MHz, I guess the limitation is on the
processor that is populated on the board. If the IGEP board comes with
OMAP3530 should work at 166MHz, if comes with DM3730 can work at
200MHz.

Cheers,
   Enric