[U-Boot] [PATCH] DaVinci DA8xx: fix set_cpu_clk_info()

[Prabhakar Lad]

Hi Laurence,

Thanks for the patch. I have tested this patch, below are few comments.

On Fri, Jul 27, 2012 at 4:19 PM, Laurence Withers <lwithers at guralp.com> wrote:
> For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
> initialising the DSP frequency, leading to 'bdinfo' command output such as:
>
>   [...snip...]
>   ARM frequency = 300 MHz
>   DSP frequency = -536870913 MHz
>   DDR frequency = 300 MHz
>
> This commit provides a separate implementation of set_cpu_clk_info() for
> the DA8xx SoCs that initialises the DSP frequency to zero (since
> currently the DSP is not enabled by U-Boot on any DA8xx platform). The
> separate implementation is justified because there is no common code
> between DA8xx and the other SoC families. It is now much easier to
> understand the flow of the two separate functions.
>
> Signed-off-by: Laurence Withers <lwithers at guralp.com>
> Cc: Tom Rini <trini at ti.com>
> Cc: Hadli, Manjunath <manjunath.hadli at ti.com>
> Cc: Heiko Schocher <hs at denx.de>
> ---
>  arch/arm/cpu/arm926ejs/davinci/cpu.c |   21 +++++++++++++--------
>  1 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
> index 6cb857a..4bdb08b 100644
> --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
> +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
> @@ -117,6 +117,16 @@ int clk_get(enum davinci_clk_ids id)
>  out:
>         return pll_out;
>  }
> +
> +int set_cpu_clk_info(void)
> +{
> +       gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
> +       /* DDR PHY uses an x2 input clock */
> +       gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;

     Can you define a macro for this 0x10001 ?

    With that change you can add my ACK:
Acked-by: Prabhakar Lad <prabhakar.lad at ti.com>

Thx,
--Prabhakar Lad

> +       gd->bd->bi_dsp_freq = 0;
> +       return 0;
> +}
> +
>  #else /* CONFIG_SOC_DA8XX */
>
>  static unsigned pll_div(volatile void *pllbase, unsigned offset)
> @@ -187,16 +197,9 @@ unsigned int davinci_clk_get(unsigned int div)
>         return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
>  }
>  #endif
> -#endif /* !CONFIG_SOC_DA8XX */
>
>  int set_cpu_clk_info(void)
>  {
> -#ifdef CONFIG_SOC_DA8XX
> -       gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
> -       /* DDR PHY uses an x2 input clock */
> -       gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
> -#else
> -
>         unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
>  #if defined(CONFIG_SOC_DM365)
>         pllbase = DAVINCI_PLL_CNTRL1_BASE;
> @@ -215,10 +218,12 @@ int set_cpu_clk_info(void)
>         pllbase = DAVINCI_PLL_CNTRL0_BASE;
>  #endif
>         gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
> -#endif
> +
>         return 0;
>  }
>
> +#endif /* !CONFIG_SOC_DA8XX */
> +
>  /*
>   * Initializes on-chip ethernet controllers.
>   * to override, implement board_eth_init()
> --
> 1.7.2.5
>
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