[U-Boot] [PATCH 18/17] am33xx: Correct and clean up ddr_regs struct
Tom Rini
trini at ti.com
Mon Jul 30 21:29:45 CEST 2012
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.
Signed-off-by: Tom Rini <trini at ti.com>
---
arch/arm/cpu/armv7/am33xx/ddr.c | 7 +----
arch/arm/cpu/armv7/am33xx/emif4.c | 10 +-------
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 37 +++++++++++++--------------
3 files changed, 20 insertions(+), 34 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 59ca51f..bceed81 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -77,20 +77,14 @@ void config_ddr_phy(const struct emif_regs *regs)
void config_cmd_ctrl(const struct cmd_control *cmd)
{
writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
- writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
- writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
- writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
- writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
- writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
- writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
}
@@ -106,6 +100,7 @@ void config_ddr_data(int macrono, const struct ddr_data *data)
writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
+ writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index ace3d26..3bb91d3 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -61,25 +61,20 @@ static const struct ddr_data ddr2_data = {
|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+ .datauserank0delay = DDR2_PHY_RANK0_DELAY,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = DDR2_RATIO,
- .cmd0csforce = CMD_FORCE,
- .cmd0csdelay = CMD_DELAY,
.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
.cmd0iclkout = DDR2_INVERT_CLKOUT,
.cmd1csratio = DDR2_RATIO,
- .cmd1csforce = CMD_FORCE,
- .cmd1csdelay = CMD_DELAY,
.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
.cmd1iclkout = DDR2_INVERT_CLKOUT,
.cmd2csratio = DDR2_RATIO,
- .cmd2csforce = CMD_FORCE,
- .cmd2csdelay = CMD_DELAY,
.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
.cmd2iclkout = DDR2_INVERT_CLKOUT,
};
@@ -121,9 +116,6 @@ void config_ddr(short ddr_type)
config_ddr_data(0, &ddr2_data);
config_ddr_data(1, &ddr2_data);
- writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
- writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
-
config_io_ctrl(DDR2_IOCTRL_VALUE);
/* Set CKE to be controlled by EMIF/DDR PHY */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index b37b161..0526863 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -26,8 +26,6 @@
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
-#define CMD_FORCE 0x00
-#define CMD_DELAY 0x00
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
@@ -66,43 +64,43 @@ void config_ddr_phy(const struct emif_regs *regs);
/**
* This structure represents the DDR registers on AM33XX devices.
+ * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
+ * correspond to DATA1 registers defined here.
*/
struct ddr_regs {
unsigned int resv0[7];
unsigned int cm0csratio; /* offset 0x01C */
- unsigned int cm0csforce; /* offset 0x020 */
- unsigned int cm0csdelay; /* offset 0x024 */
+ unsigned int resv1[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int cm0iclkout; /* offset 0x02C */
- unsigned int resv1[8];
+ unsigned int resv2[8];
unsigned int cm1csratio; /* offset 0x050 */
- unsigned int cm1csforce; /* offset 0x054 */
- unsigned int cm1csdelay; /* offset 0x058 */
+ unsigned int resv3[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int cm1iclkout; /* offset 0x060 */
- unsigned int resv2[8];
+ unsigned int resv4[8];
unsigned int cm2csratio; /* offset 0x084 */
- unsigned int cm2csforce; /* offset 0x088 */
- unsigned int cm2csdelay; /* offset 0x08C */
+ unsigned int resv5[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int cm2iclkout; /* offset 0x094 */
- unsigned int resv3[12];
+ unsigned int resv6[12];
unsigned int dt0rdsratio0; /* offset 0x0C8 */
- unsigned int resv4[4];
+ unsigned int resv7[4];
unsigned int dt0wdsratio0; /* offset 0x0DC */
- unsigned int resv5[4];
+ unsigned int resv8[4];
unsigned int dt0wiratio0; /* offset 0x0F0 */
- unsigned int resv6;
+ unsigned int resv9;
+ unsigned int dt0wimode0; /* offset 0x0F8 */
unsigned int dt0giratio0; /* offset 0x0FC */
- unsigned int resv7[2];
+ unsigned int resv10;
+ unsigned int dt0gimode0; /* offset 0x104 */
unsigned int dt0fwsratio0; /* offset 0x108 */
- unsigned int resv8[5];
+ unsigned int resv11[4];
+ unsigned int dt0dqoffset; /* offset 0x11C */
unsigned int dt0wrsratio0; /* offset 0x120 */
- unsigned int resv9[4];
+ unsigned int resv12[4];
unsigned int dt0rdelays0; /* offset 0x134 */
unsigned int dt0dldiff0; /* offset 0x138 */
- unsigned int resv10[39];
- unsigned int dt1rdelays0; /* offset 0x1D8 */
};
/**
@@ -136,6 +134,7 @@ struct ddr_data {
unsigned long datagiratio0;
unsigned long datafwsratio0;
unsigned long datawrsratio0;
+ unsigned long datauserank0delay;
unsigned long datadldiff0;
};
--
1.7.9.5
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