[U-Boot] [PATCH v2 1/4] DaVinci DA8xx: tidy up clock ID definition

[Laurence Withers]

Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.

Signed-off-by: Laurence Withers <lwithers at guralp.com>
Cc: Tom Rini <trini at ti.com>
Cc: Prabhakar Lad <prabhakar.csengg at gmail.com>
---
Changes in v2:
 - Re-ordered patch series to tidy up clock IDs before tidying up users
   (set_cpu_clk_info()).
---
 arch/arm/include/asm/arch-davinci/hardware.h |   53 +++++++++++++++++++-------
 1 files changed, 39 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..dac43bb 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -441,21 +441,46 @@ struct davinci_pllc_regs {
 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
 #define DAVINCI_PLLC_DIV_MASK	0x1f
 
-#define ASYNC3          get_async3_src()
-#define PLL1_SYSCLK2		((1 << 16) | 0x2)
-#define DAVINCI_SPI1_CLKID  (cpu_is_da830() ? 2 : ASYNC3)
-/* Clock IDs */
+/*
+ * A clock ID is a 32-bit number where bit 16 represents the PLL controller
+ * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
+ * counting from 1. Clock IDs may be passed to clk_get().
+ */
+
+/* flags to select PLL controller */
+#define DAVINCI_PLLC0_FLAG			(0)
+#define DAVINCI_PLLC1_FLAG			(1 << 16)
+
 enum davinci_clk_ids {
-	DAVINCI_SPI0_CLKID = 2,
-	DAVINCI_UART2_CLKID = 2,
-	DAVINCI_MMC_CLKID = 2,
-	DAVINCI_MDIO_CLKID = 4,
-	DAVINCI_ARM_CLKID = 6,
-	DAVINCI_PLLM_CLKID = 0xff,
-	DAVINCI_PLLC_CLKID = 0x100,
-	DAVINCI_AUXCLK_CLKID = 0x101
+	/*
+	 * Clock IDs for PLL outputs. Each may be switched on/off independently,
+	 * and each may map to one or more peripherals.
+	 */
+	DAVINCI_PLL0_SYSCLK2			= DAVINCI_PLLC0_FLAG | 2,
+	DAVINCI_PLL0_SYSCLK4			= DAVINCI_PLLC0_FLAG | 4,
+	DAVINCI_PLL0_SYSCLK6			= DAVINCI_PLLC0_FLAG | 6,
+	DAVINCI_PLL1_SYSCLK2			= DAVINCI_PLLC1_FLAG | 2,
+
+	/* map peripherals to clock IDs */
+	DAVINCI_ARM_CLKID			= DAVINCI_PLL0_SYSCLK6,
+	DAVINCI_MDIO_CLKID			= DAVINCI_PLL0_SYSCLK4,
+	DAVINCI_MMC_CLKID			= DAVINCI_PLL0_SYSCLK2,
+	DAVINCI_SPI0_CLKID			= DAVINCI_PLL0_SYSCLK2,
+	DAVINCI_UART2_CLKID			= DAVINCI_PLL0_SYSCLK2,
+
+	/* special clock ID - output of PLL multiplier */
+	DAVINCI_PLLM_CLKID			= 0x0FF,
+
+	/* special clock ID - output of PLL post divisor */
+	DAVINCI_PLLC_CLKID			= 0x100,
+
+	/* special clock ID - PLL bypass */
+	DAVINCI_AUXCLK_CLKID			= 0x101,
 };
 
+#define DAVINCI_SPI1_CLKID	(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+						: get_async3_src())
+
 int clk_get(enum davinci_clk_ids id);
 
 /* Boot config */
@@ -570,10 +595,10 @@ static inline int cpu_is_da850(void)
 	return ((part_no == 0xb7d1) ? 1 : 0);
 }
 
-static inline int get_async3_src(void)
+static inline enum davinci_clk_ids get_async3_src(void)
 {
 	return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
-			PLL1_SYSCLK2 : 2;
+			DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
 }
 
 #endif /* CONFIG_SOC_DA8XX */
-- 
1.7.2.5