[U-Boot] [PATCH v3 2/9] da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVM

[Christian Riesch]

Hi Prabhakar,

On Thu, Jun 21, 2012 at 9:51 AM, Prabhakar Lad <prabhakar.lad at ti.com> wrote:
> From: Rajashekhara, Sudhakar <sudhakar.raj at ti.com>
>
> AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
> MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When
> GP0[11] is low, the SD0 interface will not work, but NOR
> flash will. When GP0[11] is high, SD0 will work but NOR
> flash will not.
>
> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj at ti.com>
> Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
> Signed-off-by: Hadli, Manjunath <manjunath.hadli at ti.com>
> ---
>  board/davinci/da8xxevm/da850evm.c |   12 +++++++++++-
>  1 files changed, 11 insertions(+), 1 deletions(-)
>
> diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
> index 88337ff..0d75b84 100644
> --- a/board/davinci/da8xxevm/da850evm.c
> +++ b/board/davinci/da8xxevm/da850evm.c
> @@ -335,7 +335,7 @@ int board_early_init_f(void)
>
>  int board_init(void)
>  {
> -#ifdef CONFIG_USE_NOR
> +#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC)
>        u32 val;
>  #endif
>
> @@ -386,6 +386,16 @@ int board_init(void)
>        writel(val, GPIO_BANK0_REG_CLR_ADDR);
>  #endif
>
> +#ifdef CONFIG_DAVINCI_MMC
> +       /* Set the GPIO direction as output */
> +       clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));

big endian? I think you want clrbits_le32.

Regards, Christian

> +
> +       /* Set the output as high */
> +       val = readl(GPIO_BANK0_REG_SET_ADDR);
> +       val |= (0x01 << 11);
> +       writel(val, GPIO_BANK0_REG_SET_ADDR);
> +#endif
> +
>  #ifdef CONFIG_DRIVER_TI_EMAC
>        davinci_emac_mii_mode_sel(HAS_RMII);
>  #endif /* CONFIG_DRIVER_TI_EMAC */
> --
> 1.7.4.1
>
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