[U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

[Marek Vasut]

This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM properly. The
other option is to use bounce buffer, but that involves a
lot of copying and therefore degrades performance rapidly.
Therefore disallow this possibility of unaligned load address
altogether if data cache is on.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Scott Wood <scottwood at freescale.com>
---
 common/cmd_nand.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index a91ccf4..122a91c 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -609,6 +609,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 			goto usage;
 
 		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+		if (!cacheline_aligned(addr))
+			return 1;
 
 		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
 		printf("\nNAND %s: ", read ? "read" : "write");
@@ -924,6 +926,9 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 				addr = simple_strtoul(argv[1], NULL, 16);
 			else
 				addr = CONFIG_SYS_LOAD_ADDR;
+			if (!cacheline_aligned(addr))
+				return 1;
+
 			return nand_load_image(cmdtp, &nand_info[dev->id->num],
 					       part->offset, addr, argv[0]);
 		}
@@ -956,6 +961,10 @@ usage:
 		bootstage_error(BOOTSTAGE_ID_NAND_SUFFIX);
 		return CMD_RET_USAGE;
 	}
+
+	if (!cacheline_aligned(addr))
+		return 1;
+
 	bootstage_mark(BOOTSTAGE_ID_NAND_SUFFIX);
 
 	if (!boot_device) {
-- 
1.7.10