[U-Boot] [PATCH v8] usb: align buffers at cacheline

[Mike Frysinger]

On Monday 05 March 2012 09:46:21 Puneet Saxena wrote:
> As DMA expects the buffers to be equal and larger then
> cache lines, This aligns buffers at cacheline.

i don't think this statement is true.  DMA doesn't care about alignment (well, 
some do, but it's not related to cache lines but rather some other restriction 
in the peripheral DMA itself).  what does matter is that cache operations 
operate on cache lines and not individual bytes.  hence the core arm code was 
updated to warn when someone told it to invalidate X bytes but the hardware 
literally could not, so it had to invalidate X + Y bytes.

> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
>
>  static void flush_invalidate(u32 addr, int size, int flush)
>  {
> +	/*
> +	 * Size is the bytes actually moved during transaction,
> +	 * which may not equal to the cache line. This results
> +	 * stop address passed for invalidating cache may not be aligned.
> +	 * Therfore making size as multiple of cache line size.
> +	 */
> +	size = ALIGN(size, ARCH_DMA_MINALIGN);
> +
>  	if (flush)
>  		flush_dcache_range(addr, addr + size);
>  	else

i think this is wrong and merely hides the errors from higher up instead of 
fixing them.  the point of the warning was to tell you that the code was 
invalidating *too many* bytes.  this code still invalidates too many bytes 
without any justification as for why it's OK to do here.  further, this code 
path only matters to the invalidation logic, not the flush logic.
-mike
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