[U-Boot] RFC - how to support multipl DRAM chips in a single SPL build?

[Peter Barada]

I'm trying to build a single SPL/u-boot that supports multiple Logic
OMAP 35x/37x boards, with multiple configurations of DRAM/NAND/NOR. 
This is to make our support/production much simpler, and allow one
SPL/u-boot "just work" on all or various boards.  To do so I need to
figure out:

1) Probe for different DDR/NAND chips

Our boards have multiple PoP parts on them (e.g. MT46H128M32L2K1-5 512MB
DDR/0MB NAND, MT29C4G48MAPLCJI6 256MB DDR/512MB NAND,
H8KCS0SJ0AER_MT29C2G24MAKLAJG6 128MB DDR/256MB NAND, etc), and no clear
way in SPL to pick the right timings.  In my current x-loader code I
have a table of SDRC register settings, set them up, and then probe to
see if memory exists (including holes), and if a configuration doesn't
work then move onto the next set of SDRC settings and try again.

2) Probe for multiple configurations of NOR/NAND

Our boards can be populated with PoP/NOR flash in multiple combinations
including cases where NAND+NOR exist, NAND or NOR exist, or neither NAND
or NOR exist.  Currently u-boot has a static belief (driven by
CONFIG_ENV_IS_*) of whether NAND/NOR exist and where to load/store the
environment.  If the runtime detection is inconsistent with u-boot's
configuration u-boot wedges due to accessing incomplete structures (i.e.
nand_info[0].block_isbad is NULL if no NAND is found causing u-boot to
go off in the weeds).


I currently have x-loader/u-boot code that does this, but want to
identify an approach for doing this in the current u-boot trees(and
incorporate such changes), such that it doesn't break other
boards/archs, but also minimize impact on SPL/u-boot size...

Any suggestions on an approach are much appreciated!

-- 
Peter Barada
peter.barada at logicpd.com