[U-Boot] [PATCH V3] net: fec_mxc: allow use with cache enabled

Eric Nelson eric.nelson at boundarydevices.com
Wed Mar 14 20:12:10 CET 2012

On 03/13/2012 10:41 PM, Mike Frysinger wrote:
> On Wednesday 14 March 2012 01:12:38 Eric Nelson wrote:
>> Most of the PPC devices seem to have values of 16 or 32
>> for ARCH_DMA_MINALIGN, but PPC64BRIDGE and E500MC would
>> have a problem if their drivers don't implement a bounce
>> buffer because PKTALIGN<  ARCH_DMA_MINALIGN.
>> (see arch/powerpc/include/asm/cache.h)
>> This condition is properly tested for in fec_mxc.c.
> so fix this in common code instead of hacking around it in individual drivers.
> seems to me that PKTALIGN should be defined to ARCH_DMA_MINALIGN and ultimately
> removed.
> -mike

Hi Mike,

I'm not in a position to test against MAKEALL, but it appears that all
architectures have cache.h and define ARCH_DMA_MINALIGN, so it should
be trivially easy to fix PKTALIGN to be at least ARCH_DMA_MINALIGN as
shown below.

PKTSIZE_ALIGN seems safe for all architectures at 1536.

Note that this will reduce the value to 16 for some PPC devices, but I
haven't found any place that this would break things.

Is this what you're after?

Are you in a position to run MAKEALL or can you advise about the

Please advise,


~/u-boot-imx6$ git diff
diff --git a/include/net.h b/include/net.h
index e4d42c2..ff428d0 100644
--- a/include/net.h
+++ b/include/net.h
@@ -16,6 +16,7 @@
  #include <commproc.h>
  #endif /* CONFIG_8xx */

+#include <asm/cache.h>
  #include <asm/byteorder.h>     /* for nton* / ntoh* stuff */

@@ -31,7 +32,7 @@
  # define PKTBUFSRX     4

-#define PKTALIGN       32

  /* IPv4 addresses are always 32 bits in size */
  typedef u32            IPaddr_t;

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