[U-Boot] [PATCH 1/1] MX53: DDR: Fix ZQHWCTRL field TZQ_CS

[Troy Kisky]

On 3/22/2012 3:00 PM, Troy Kisky wrote:
> Currently, board files are setting this field to 0x01
> which the manual says is a reserved value. Change to
> use the default of 0x04 - 128 cycles.
Typo, should say default of 0x02 - 128 cycles

>
> Signed-off-by: Troy Kisky<troy.kisky at boundarydevices.com>
> ---
>   board/freescale/mx53ard/imximage_dd3.cfg |    2 +-
>   board/freescale/mx53evk/imximage.cfg     |    2 +-
>   board/freescale/mx53loco/imximage.cfg    |    2 +-
>   board/freescale/mx53smd/imximage.cfg     |    2 +-
>   4 files changed, 4 insertions(+), 4 deletions(-)
>
>
>
>
> I've tested on an mx53, but this needs much more
> testing before being applied.
>
>