[U-Boot] [PATCH 1/1] MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Stefano Babic sbabic at denx.de
Fri Mar 23 10:34:18 CET 2012

On 23/03/2012 04:25, Troy Kisky wrote:
> On 3/22/2012 6:47 PM, Troy Kisky wrote:
>> On 3/22/2012 3:00 PM, Troy Kisky wrote:
>>> Currently, board files are setting this field to 0x01
>>> which the manual says is a reserved value. Change to
>>> use the default of 0x04 - 128 cycles.
>> Typo, should say default of 0x02 - 128 cycles
> Possibly the manual is wrong, and the value of 0x01 corresponds
> to 64 cycles? My testing was on a DDR2 device where this field
> is not relevant.

Is there someone who can answer to this question ? This patch fixes the
value according to the manual, without doubts. But if the manual is wrong...

Best regards,
Stefano Babic

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de

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