[U-Boot] [PATCH 4/4][v2] powerpc/85xx:Fix NAND code base to support debugger

[Prabhakar Kushwaha]

Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu at freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
  Based upon git://git.denx.de/u-boot.git branch master

  Changes for v2: 
	- Removed unnecessary CONFIG_E500
	- Avoid TLB creation for NAND_SPL

 Tested on
  - SoC having E500 Family processor (P1010RDB, BSC9131RDB)
  - SoC having E500MC Family processor (P4080DS, P3041DS)

 arch/powerpc/cpu/mpc85xx/start.S |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 1cfd08a..92d65af 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -182,7 +182,7 @@ l2_disabled:
 	andi.	r1,r3,L1CSR0_DCE at l
 	beq	2b
 
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
 /*
  * TLB entry for debuggging in AS1
  * Create temporary TLB entry in AS0 to handle debug exception
@@ -1437,17 +1437,25 @@ relocate_code:
 7:	sync			/* Wait for all icbi to complete on bus */
 	isync
 
-	/*
-	 * Re-point the IVPR at RAM
-	 */
-	mtspr	IVPR,r10
-
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 
 	addi	r0,r10,in_ram - _start + _START_OFFSET
+
+#if defined(CONFIG_NAND_SPL)
+/*
+ * As IVPR is going to point RAM address,
+ * Make sure IVOR15 has valid opcode to support debugger
+ */
+	mtspr	IVOR15,r0
+#endif
+	/*
+	 * Re-point the IVPR at RAM
+	 */
+	mtspr	IVPR,r10
+
 	mtlr	r0
 	blr				/* NEVER RETURNS! */
 	.globl	in_ram
-- 
1.7.5.4