[U-Boot] [PATCH 1/2] FSL/eSDHC: enable the peripheral clock to detect the card

[Huang Changming-R66093]

Thanks
Jerry Huang


> -----Original Message-----
> From: Stefano Babic [mailto:sbabic at denx.de]
> Sent: Wednesday, March 28, 2012 1:13 AM
> To: Huang Changming-R66093
> Cc: u-boot at lists.denx.de; Andy Fleming
> Subject: Re: [U-Boot] [PATCH 1/2] FSL/eSDHC: enable the peripheral clock
> to detect the card
> 
> On 27/03/2012 12:25, Chang-Ming.Huang at freescale.com wrote:
> > From: Jerry Huang <Chang-Ming.Huang at freescale.com>
> >
> > According to the card detection of p1/p2 paltform RM, we should set
> > SYSCTL[PEREN] to enable the clock.
> > Otherwise, after booting the u-boot, and then inserting the SD card,
> > the SD card can't be detected.
> >
> > Signed-off-by: Jerry Huang <Chang-Ming.Huang at freescale.com>
> > CC: Andy Fleming <afleming at gmail.com>
> > ---
> 
> Hi Jerry,
> 
> >  drivers/mmc/fsl_esdhc.c |    2 ++
> >  1 files changed, 2 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > a2f35e3..1682a79 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -491,6 +491,8 @@ int fsl_esdhc_initialize(bd_t *bis, struct
> fsl_esdhc_cfg *cfg)
> >  	/* First reset the eSDHC controller */
> >  	esdhc_reset(regs);
> >
> > +	esdhc_write32(&regs->sysctl, SYSCTL_PEREN);
> > +
> 
> You add this setup to all architectures: PQIII, i.MX5, i.MX6. Is it what
> you really want ?
In fact, this field is set in function 'set_sysctl', too.
In order to detect the card, I just reset it in initialize stage.

For p1/p2, the field SYSCTL[PEREN](bit29) is needed to enable the peripheral clock before
Detecting the SD card.
For p3041, this field is reserved, I think I.MX5 and I.MX6 has the same setting.
And I have tested this field on p3041, accessing this field has no any impact for SD controller.

In fact, you can find out, the driver fsl_esdh.c is first wrote for p1/p2 (has PEREN/KCKEN/IPGEN, bit29/30/31),
i.MXx/PQIII just reuses it, and some registers have difference setting, such as SYSCRL[29, 30, 31] for p1/p2,
they are reserved for p3041.