[U-Boot] [PATCH V2] i.MX: fsl_esdhc: allow use with cache enabled.

[Andy Fleming]

> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
>                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
>                esdhc_write32(&regs->dsaddr, (u32)data->dest);
>        } else {
> +               flush_dcache_range((ulong)data->src,
> +                                  (ulong)data->src+data->blocks
> +                                        *data->blocksize);
> +


This still won't work. I don't believe this is implemented at all on
the FSL PowerPC parts that use this controller.

At the very least, it needs to be protected by an ifdef.


>                if (wml_value > WML_WR_WML_MAX)
>                        wml_value = WML_WR_WML_MAX_VAL;
>                if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
> @@ -249,7 +253,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
>        return 0;
>  }
>
> -
> +static void check_and_invalidate_dcache_range
> +       (struct mmc_cmd *cmd,
> +        struct mmc_data *data) {


This is non-standard formatting in U-Boot.


Andy