[U-Boot] [PATCH 1/2] MSM7x27a:Add support for interrupt
Srikanth Reddy Vintha
srikanth.reddy at lntinfotech.com
Fri May 11 08:54:21 CEST 2012
* support for msm7x27a interrupt
Signed-off-by: Srikanth Reddy Vintha <srikanth.reddy at lntinfotech.com>
---
arch/arm/cpu/armv7/msm7x27a/Makefile | 1 +
arch/arm/cpu/armv7/msm7x27a/interrupts.c | 136 +++++++++++++++++++++++
arch/arm/include/asm/arch-msm7x27a/exclusion.h | 42 +++++++
arch/arm/include/asm/arch-msm7x27a/interrupts.h | 39 +++++++
arch/arm/include/asm/arch-msm7x27a/irqs.h | 98 ++++++++++++++++
board/qcom/msm7x27a_surf/msm7x27a_surf.c | 2 +
include/configs/msm7x27a_surf.h | 2 +-
7 files changed, 319 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/armv7/msm7x27a/interrupts.c
create mode 100644 arch/arm/include/asm/arch-msm7x27a/exclusion.h
create mode 100644 arch/arm/include/asm/arch-msm7x27a/interrupts.h
create mode 100644 arch/arm/include/asm/arch-msm7x27a/irqs.h
diff --git a/arch/arm/cpu/armv7/msm7x27a/Makefile b/arch/arm/cpu/armv7/msm7x27a/Makefile
index 5f493d7..19e7546 100644
--- a/arch/arm/cpu/armv7/msm7x27a/Makefile
+++ b/arch/arm/cpu/armv7/msm7x27a/Makefile
@@ -34,6 +34,7 @@ COBJS-y := board.o
COBJS-y += timer.o
COBJS-y += acpuclock.o
COBJS-y += gpio.o
+COBJS-$(CONFIG_USE_IRQ) += interrupts.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
diff --git a/arch/arm/cpu/armv7/msm7x27a/interrupts.c b/arch/arm/cpu/armv7/msm7x27a/interrupts.c
new file mode 100644
index 0000000..cc45c4b
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7x27a/interrupts.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/interrupts.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/exclusion.h>
+
+#define VIC_REG(off) (MSM_VIC_BASE + (off))
+
+#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_EN0 VIC_REG(0x0010)
+#define VIC_INT_EN1 VIC_REG(0x0014)
+#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
+#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
+#define VIC_INT_ENSET0 VIC_REG(0x0030)
+#define VIC_INT_ENSET1 VIC_REG(0x0034)
+#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
+#define VIC_NO_PEND_VAL VIC_REG(0x0060)
+#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
+#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
+#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
+#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
+#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
+#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
+#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
+#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
+#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
+#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
+#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
+#define VIC_SOFTINT0 VIC_REG(0x00C0)
+#define VIC_SOFTINT1 VIC_REG(0x00C4)
+#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
+#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
+#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
+#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
+#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
+#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
+
+struct ihandler {
+ int_handler func;
+ void *arg;
+};
+
+static struct ihandler handler[NR_IRQS];
+
+int arch_interrupt_init(void)
+{
+ writel(0xffffffff, VIC_INT_CLEAR0);
+ writel(0xffffffff, VIC_INT_CLEAR1);
+ writel(0, VIC_INT_SELECT0);
+ writel(0, VIC_INT_SELECT1);
+ writel(0xffffffff, VIC_INT_TYPE0);
+ writel(0xffffffff, VIC_INT_TYPE1);
+ writel(0, VIC_CONFIG);
+ writel(1, VIC_INT_MASTEREN);
+ return 0;
+}
+
+void do_irq(struct pt_regs *pt_regs)
+{
+ unsigned num;
+ num = readl(VIC_IRQ_VEC_RD);
+ num = readl(VIC_IRQ_VEC_PEND_RD);
+ if (num > NR_IRQS)
+ return;
+ (void) handler[num].func(handler[num].arg);
+ writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
+ writel(0, VIC_IRQ_VEC_WR);
+}
+
+int mask_interrupt(unsigned int vector)
+{
+ unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
+ unsigned bit = 1 << (vector & 31);
+ writel(bit, reg);
+ return 0;
+}
+
+int unmask_interrupt(unsigned int vector)
+{
+ unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
+ unsigned bit = 1 << (vector & 31);
+ writel(bit, reg);
+ return 0;
+}
+
+void register_int_handler(unsigned int vector, int_handler func, void *arg)
+{
+ if (vector >= NR_IRQS) {
+ debug("Could not set interrupt %#08x", vector);
+ return;
+ }
+ enter_critical_section();
+ handler[vector].func = func;
+ handler[vector].arg = arg;
+ exit_critical_section();
+}
+
diff --git a/arch/arm/include/asm/arch-msm7x27a/exclusion.h b/arch/arm/include/asm/arch-msm7x27a/exclusion.h
new file mode 100644
index 0000000..e98716e
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/exclusion.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __EXCLUSION_H
+#define __EXCLUSION_H
+#include <common.h>
+
+/* critical sections */
+extern int critical_section_count;
+
+static inline __attribute__((always_inline)) void enter_critical_section(void)
+{
+ critical_section_count++;
+ if (critical_section_count == 1)
+ disable_interrupts();
+}
+
+static inline __attribute__((always_inline)) void exit_critical_section(void)
+{
+ critical_section_count--;
+ if (critical_section_count == 0)
+ enable_interrupts();
+}
+
+#endif
diff --git a/arch/arm/include/asm/arch-msm7x27a/interrupts.h b/arch/arm/include/asm/arch-msm7x27a/interrupts.h
new file mode 100644
index 0000000..c8e0368
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/interrupts.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2008 Travis Geiselbrecht
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __PLATFORM_INTERRUPTS_H
+#define __PLATFORM_INTERRUPTS_H
+
+enum handler_return {
+ INT_NO_RESCHEDULE = 0,
+ INT_RESCHEDULE,
+};
+
+typedef enum handler_return (*int_handler)(void *arg);
+
+void register_int_handler(unsigned int vector, int_handler handler, void *arg);
+int mask_interrupt(unsigned int vector);
+int unmask_interrupt(unsigned int vector);
+#endif
diff --git a/arch/arm/include/asm/arch-msm7x27a/irqs.h b/arch/arm/include/asm/arch-msm7x27a/irqs.h
new file mode 100644
index 0000000..868d185
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/irqs.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSM7K_IRQS_H_
+#define _PLATFORM_MSM7K_IRQS_H_
+
+#define INT_A9_M2A_0 0
+#define INT_A9_M2A_1 1
+#define INT_A9_M2A_2 2
+#define INT_A9_M2A_3 3
+#define INT_A9_M2A_4 4
+#define INT_A9_M2A_5 5
+#define INT_A9_M2A_6 6
+#define INT_GP_TIMER_EXP 7
+#define INT_DEBUG_TIMER_EXP 8
+#define INT_UART1 9
+#define INT_UART2 10
+#define INT_UART3 11
+#define INT_UART1_RX 12
+#define INT_UART2_RX 13
+#define INT_UART3_RX 14
+#define INT_USB_OTG 15
+#define INT_MDDI_PRI 16
+#define INT_MDDI_EXT 17
+#define INT_MDDI_CLIENT 18
+#define INT_MDP 19
+#define INT_GRAPHICS 20
+#define INT_ADM_AARM 21
+#define INT_ADSP_A11 22
+#define INT_ADSP_A9_A11 23
+#define INT_SDC1_0 24
+#define INT_SDC1_1 25
+#define INT_SDC2_0 26
+#define INT_SDC2_1 27
+#define INT_KEYSENSE 28
+#define INT_TCHSCRN_SSBI 29
+#define INT_TCHSCRN1 30
+#define INT_TCHSCRN2 31
+
+#define INT_GPIO_GROUP1 (32 + 0)
+#define INT_GPIO_GROUP2 (32 + 1)
+#define INT_PWB_I2C (32 + 2)
+#define INT_NAND_WR_ER_DONE (32 + 3)
+#define INT_NAND_OP_DONE (32 + 4)
+#define INT_SOFTRESET (32 + 5)
+#define INT_PBUS_ARM11 (32 + 6)
+#define INT_AXI_MPU_SMI (32 + 7)
+#define INT_AXI_MPU_EBI1 (32 + 8)
+#define INT_AD_HSSD (32 + 9)
+#define INT_ARM11_PM (32 + 10)
+#define INT_ARM11_DMA (32 + 11)
+#define INT_TSIF_IRQ (32 + 12)
+#define INT_UART1DM_IRQ (32 + 13)
+#define INT_UART1DM_RX (32 + 14)
+#define INT_USB_HS (32 + 15)
+#define INT_SDC3_0 (32 + 16)
+#define INT_SDC3_1 (32 + 17)
+#define INT_SDC4_0 (32 + 18)
+#define INT_SDC4_1 (32 + 19)
+#define INT_UART2DM_RX (32 + 20)
+#define INT_UART2DM_IRQ (32 + 21)
+
+#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
+
+#define NR_IRQS 54
+
+#endif
diff --git a/board/qcom/msm7x27a_surf/msm7x27a_surf.c b/board/qcom/msm7x27a_surf/msm7x27a_surf.c
index 9199f48..cc8f000 100644
--- a/board/qcom/msm7x27a_surf/msm7x27a_surf.c
+++ b/board/qcom/msm7x27a_surf/msm7x27a_surf.c
@@ -29,11 +29,13 @@
#include <asm/arch/proc_comm.h>
#include "msm7x27a_surf.h"
+int critical_section_count;
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f()
{
+ critical_section_count = 0;
uart1_clock_init();
return 0;
}
diff --git a/include/configs/msm7x27a_surf.h b/include/configs/msm7x27a_surf.h
index a82ba59..2b5efb8 100644
--- a/include/configs/msm7x27a_surf.h
+++ b/include/configs/msm7x27a_surf.h
@@ -98,7 +98,7 @@
/*---------------------------------------------------------------------
* IRQ Settings
*/
-
+#define CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
--
1.7.1
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