[U-Boot] [PATCH v2] sh: Add SH7269 device and RSK2+SH7269 board
Nobuhiro Iwamatsu
iwamatsu at nigauri.org
Tue May 22 03:52:33 CEST 2012
Hi. Phil.
Applied. Thank you.
Best regards,
Nobuhiro
2012/5/16 Phil Edworthy <phil.edworthy at renesas.com>:
> This is an sh2a device (max 266MHz) with FPU, video display
> controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports,
> SD and on-chip USB.
>
> The RSK2+SH7269 board uses the SH7269 processor. It is often
> referred to as just rsk7269.
>
> Signed-off-by: Phil Edworthy <phil.edworthy at renesas.com>
> ---
> v2: added more info in the commit message
>
> arch/sh/include/asm/cpu_sh2.h | 2 +
> arch/sh/include/asm/cpu_sh7269.h | 26 +++++
> board/renesas/rsk7269/Makefile | 27 +++++
> board/renesas/rsk7269/lowlevel_init.S | 182 +++++++++++++++++++++++++++++++++
> board/renesas/rsk7269/rsk7269.c | 73 +++++++++++++
> boards.cfg | 1 +
> drivers/serial/serial_sh.c | 4 +
> drivers/serial/serial_sh.h | 10 ++
> include/configs/rsk7269.h | 76 ++++++++++++++
> 9 files changed, 401 insertions(+), 0 deletions(-)
> create mode 100644 arch/sh/include/asm/cpu_sh7269.h
> create mode 100644 board/renesas/rsk7269/Makefile
> create mode 100644 board/renesas/rsk7269/lowlevel_init.S
> create mode 100644 board/renesas/rsk7269/rsk7269.c
> create mode 100644 include/configs/rsk7269.h
>
> diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
> index 767e189..28be591 100644
> --- a/arch/sh/include/asm/cpu_sh2.h
> +++ b/arch/sh/include/asm/cpu_sh2.h
> @@ -35,6 +35,8 @@
> # include <asm/cpu_sh7203.h>
> #elif defined(CONFIG_CPU_SH7264)
> # include <asm/cpu_sh7264.h>
> +#elif defined(CONFIG_CPU_SH7269)
> +# include <asm/cpu_sh7269.h>
> #else
> # error "Unknown SH2 variant"
> #endif
> diff --git a/arch/sh/include/asm/cpu_sh7269.h b/arch/sh/include/asm/cpu_sh7269.h
> new file mode 100644
> index 0000000..4dea708
> --- /dev/null
> +++ b/arch/sh/include/asm/cpu_sh7269.h
> @@ -0,0 +1,26 @@
> +#ifndef _ASM_CPU_SH7269_H_
> +#define _ASM_CPU_SH7269_H_
> +
> +/* Cache */
> +#define CCR1 0xFFFC1000
> +#define CCR CCR1
> +
> +/* SCIF */
> +#define SCSMR_0 0xE8007000
> +#define SCIF0_BASE SCSMR_0
> +#define SCSMR_1 0xE8007800
> +#define SCIF1_BASE SCSMR_1
> +#define SCSMR_2 0xE8008000
> +#define SCIF2_BASE SCSMR_2
> +#define SCSMR_3 0xE8008800
> +#define SCIF3_BASE SCSMR_3
> +#define SCSMR_7 0xE800A800
> +#define SCIF7_BASE SCSMR_7
> +
> +/* Timer(CMT) */
> +#define CMSTR 0xFFFEC000
> +#define CMCSR_0 0xFFFEC002
> +#define CMCNT_0 0xFFFEC004
> +#define CMCOR_0 0xFFFEC006
> +
> +#endif /* _ASM_CPU_SH7269_H_ */
> diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile
> new file mode 100644
> index 0000000..2ba04ec
> --- /dev/null
> +++ b/board/renesas/rsk7269/Makefile
> @@ -0,0 +1,27 @@
> +#
> +# Copyright (C) 2012 Renesas Electronics Europe Ltd.
> +# Copyright (C) 2012 Phil Edworthy
> +#
> +# This file is released under the terms of GPL v2 and any later version.
> +# See the file COPYING in the root directory of the source tree for details.
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = lib$(BOARD).o
> +
> +OBJS := rsk7269.o
> +SOBJS := lowlevel_init.o
> +
> +LIB := $(addprefix $(obj),$(LIB))
> +OBJS := $(addprefix $(obj),$(OBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> diff --git a/board/renesas/rsk7269/lowlevel_init.S b/board/renesas/rsk7269/lowlevel_init.S
> new file mode 100644
> index 0000000..399beb8
> --- /dev/null
> +++ b/board/renesas/rsk7269/lowlevel_init.S
> @@ -0,0 +1,182 @@
> +/*
> + * Copyright (C) 2012 Renesas Electronics Europe Ltd.
> + * Copyright (C) 2012 Phil Edworthy
> + * Copyright (C) 2008 Renesas Solutions Corp.
> + * Copyright (C) 2008 Nobuhiro Iwamatsu
> + *
> + * Based on board/renesas/rsk7264/lowlevel_init.S
> + *
> + * This file is released under the terms of GPL v2 and any later version.
> + * See the file COPYING in the root directory of the source tree for details.
> + */
> +#include <config.h>
> +#include <version.h>
> +
> +#include <asm/processor.h>
> +#include <asm/macro.h>
> +
> + .global lowlevel_init
> +
> + .text
> + .align 2
> +
> +lowlevel_init:
> + /* Flush and enable caches (data cache in write-through mode) */
> + write32 CCR1_A ,CCR1_D
> +
> + /* Disable WDT */
> + write16 WTCSR_A, WTCSR_D
> + write16 WTCNT_A, WTCNT_D
> +
> + /* Disable Register Bank interrupts */
> + write16 IBNR_A, IBNR_D
> +
> + /* Set clocks based on 13.225MHz xtal */
> + write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
> +
> + /* Enable all peripherals */
> + write8 STBCR3_A, STBCR3_D
> + write8 STBCR4_A, STBCR4_D
> + write8 STBCR5_A, STBCR5_D
> + write8 STBCR6_A, STBCR6_D
> + write8 STBCR7_A, STBCR7_D
> + write8 STBCR8_A, STBCR8_D
> + write8 STBCR9_A, STBCR9_D
> + write8 STBCR10_A, STBCR10_D
> +
> + /* SCIF7 and IIC2 */
> + write16 PJCR3_A, PJCR3_D /* TXD7 */
> + write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
> +
> + /* Configure bus (CS0) */
> + write16 PFCR3_A, PFCR3_D /* A24 */
> + write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
> + write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
> + write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
> + write32 CS0WCR_A, CS0WCR_D
> + write32 CS0BCR_A, CS0BCR_D
> +
> + /* Configure SDRAM (CS3) */
> + write16 PCCR2_A, PCCR2_D /* CS3# */
> + write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
> + write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
> + write32 CS3BCR_A, CS3BCR_D
> + write32 CS3WCR_A, CS3WCR_D
> + write32 SDCR_A, SDCR_D
> + write32 RTCOR_A, RTCOR_D
> + write32 RTCSR_A, RTCSR_D
> +
> + /* Configure ethernet (CS1) */
> + write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
> + write16 PHCR0_A, PHCR0_D
> + write16 PFCR2_A, PFCR2_D /* CS1# */
> + write32 CS1BCR_A, CS1BCR_D /* Big endian */
> + write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
> + write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
> + write16 PJIOR1_A, PJIOR1_D
> +
> + /* wait 200us */
> + mov.l REPEAT_D, r3
> + mov #0, r2
> +repeat0:
> + add #1, r2
> + cmp/hs r3, r2
> + bf repeat0
> + nop
> +
> + mov.l SDRAM_MODE, r1
> + mov #0, r0
> + mov.l r0, @r1
> +
> + nop
> + rts
> +
> + .align 4
> +
> +CCR1_A: .long CCR1
> +CCR1_D: .long 0x0000090B
> +
> +STBCR3_A: .long 0xFFFE0408
> +STBCR4_A: .long 0xFFFE040C
> +STBCR5_A: .long 0xFFFE0410
> +STBCR6_A: .long 0xFFFE0414
> +STBCR7_A: .long 0xFFFE0418
> +STBCR8_A: .long 0xFFFE041C
> +STBCR9_A: .long 0xFFFE0440
> +STBCR10_A: .long 0xFFFE0444
> +STBCR3_D: .long 0x0000001A
> +STBCR4_D: .long 0x00000000
> +STBCR5_D: .long 0x00000000
> +STBCR6_D: .long 0x00000000
> +STBCR7_D: .long 0x00000012
> +STBCR8_D: .long 0x00000009
> +STBCR9_D: .long 0x00000000
> +STBCR10_D: .long 0x00000010
> +
> +WTCSR_A: .long 0xFFFE0000
> +WTCNT_A: .long 0xFFFE0002
> +WTCSR_D: .word 0xA518
> +WTCNT_D: .word 0x5A00
> +
> +IBNR_A: .long 0xFFFE080E
> +IBNR_D: .word 0x0000
> +.align 2
> +FRQCR_A: .long 0xFFFE0010
> +FRQCR_D: .word 0x0015
> +.align 2
> +
> +PJCR3_A: .long 0xFFFE3908
> +PJCR3_D: .word 0x5000
> +.align 2
> +PECR1_A: .long 0xFFFE388C
> +PECR1_D: .word 0x2011
> +.align 2
> +
> +PFCR3_A: .long 0xFFFE38A8
> +PFCR2_A: .long 0xFFFE38AA
> +PBCR5_A: .long 0xFFFE3824
> +PFCR3_D: .word 0x0010
> +PFCR2_D: .word 0x0101
> +PBCR5_D: .word 0x0111
> +.align 2
> +CS0WCR_A: .long 0xFFFC0028
> +CS0WCR_D: .long 0x00000341
> +CS0BCR_A: .long 0xFFFC0004
> +CS0BCR_D: .long 0x00000400
> +
> +PCCR2_A: .long 0xFFFE384A
> +PCCR1_A: .long 0xFFFE384C
> +PCCR0_A: .long 0xFFFE384E
> +PCCR2_D: .word 0x0001
> +PCCR1_D: .word 0x1111
> +PCCR0_D: .word 0x1111
> +.align 2
> +CS3BCR_A: .long 0xFFFC0010
> +CS3BCR_D: .long 0x00004400
> +CS3WCR_A: .long 0xFFFC0034
> +CS3WCR_D: .long 0x00004912
> +SDCR_A: .long 0xFFFC004C
> +SDCR_D: .long 0x00000811
> +RTCOR_A: .long 0xFFFC0058
> +RTCOR_D: .long 0xA55A0035
> +RTCSR_A: .long 0xFFFC0050
> +RTCSR_D: .long 0xA55A0010
> +.align 2
> +SDRAM_MODE: .long 0xFFFC5460
> +REPEAT_D: .long 0x000033F1
> +
> +PHCR1_A: .long 0xFFFE38EC
> +PHCR0_A: .long 0xFFFE38EE
> +PHCR1_D: .word 0x2222
> +PHCR0_D: .word 0x2222
> +.align 2
> +CS1BCR_A: .long 0xFFFC0008
> +CS1BCR_D: .long 0x00000400
> +CS1WCR_A: .long 0xFFFC002C
> +CS1WCR_D: .long 0x00000080
> +PJDR1_A: .long 0xFFFE3914
> +PJDR1_D: .word 0x0000
> +.align 2
> +PJIOR1_A: .long 0xFFFE3910
> +PJIOR1_D: .word 0x8000
> +.align 2
> diff --git a/board/renesas/rsk7269/rsk7269.c b/board/renesas/rsk7269/rsk7269.c
> new file mode 100644
> index 0000000..842a154
> --- /dev/null
> +++ b/board/renesas/rsk7269/rsk7269.c
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright (C) 2012 Renesas Electronics Europe Ltd.
> + * Copyright (C) 2012 Phil Edworthy
> + * Copyright (C) 2008 Renesas Solutions Corp.
> + * Copyright (C) 2008 Nobuhiro Iwamatsu
> + *
> + * Based on u-boot/board/rsk7264/rsk7264.c
> + *
> + * This file is released under the terms of GPL v2 and any later version.
> + * See the file COPYING in the root directory of the source tree for details.
> + */
> +
> +#include <common.h>
> +#include <net.h>
> +#include <netdev.h>
> +#include <asm/io.h>
> +#include <asm/processor.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int checkboard(void)
> +{
> + puts("BOARD: Renesas RSK7269\n");
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
> + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
> + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
> + return 0;
> +}
> +
> +void led_set_state(unsigned short value)
> +{
> +}
> +
> +/*
> + * The RSK board has the SMSC89218 wired up 'incorrectly'.
> + * Byte-swapping is necessary, and so poor performance is inevitable.
> + * This problem cannot evade by the swap function of CHIP, this can
> + * evade by software Byte-swapping.
> + * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
> + * functions necessary to solve this problem.
> + */
> +u32 pkt_data_pull(struct eth_device *dev, u32 addr)
> +{
> + volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
> + return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
> + | swab16(*(addr_16 + 1));
> +}
> +
> +void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
> +{
> + addr += dev->iobase;
> + *(volatile u16 *)(addr + 2) = swab16((u16)val);
> + *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = 0;
> +#ifdef CONFIG_SMC911X
> + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> + return rc;
> +}
> diff --git a/boards.cfg b/boards.cfg
> index 5f328b5..b19952e 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -1009,6 +1009,7 @@ xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx
> sandbox sandbox sandbox sandbox sandbox -
> rsk7203 sh sh2 rsk7203 renesas -
> rsk7264 sh sh2 rsk7264 renesas -
> +rsk7269 sh sh2 rsk7269 renesas -
> mpr2 sh sh3 mpr2 - -
> ms7720se sh sh3 ms7720se - -
> shmin sh sh3 shmin - -
> diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
> index fcf69ab..13919c6 100644
> --- a/drivers/serial/serial_sh.c
> +++ b/drivers/serial/serial_sh.c
> @@ -35,6 +35,10 @@
> # define SCIF_BASE SCIF4_BASE
> #elif defined(CONFIG_CONS_SCIF5)
> # define SCIF_BASE SCIF5_BASE
> +#elif defined(CONFIG_CONS_SCIF6)
> +# define SCIF_BASE SCIF6_BASE
> +#elif defined(CONFIG_CONS_SCIF7)
> +# define SCIF_BASE SCIF7_BASE
> #else
> # error "Default SCIF doesn't set....."
> #endif
> diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
> index 0b3e779..da5be6f 100644
> --- a/drivers/serial/serial_sh.h
> +++ b/drivers/serial/serial_sh.h
> @@ -190,6 +190,16 @@ struct uart_port {
> # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
> # endif
> # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
> +#elif defined(CONFIG_CPU_SH7269)
> +# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
> +# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
> +# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
> +# define SCSPTR3 0xe8008820 /* 16 bit SCIF */
> +# define SCSPTR4 0xe8009020 /* 16 bit SCIF */
> +# define SCSPTR5 0xe8009820 /* 16 bit SCIF */
> +# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
> +# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
> +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
> #elif defined(CONFIG_CPU_SH7619)
> # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
> # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
> diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h
> new file mode 100644
> index 0000000..26c1764
> --- /dev/null
> +++ b/include/configs/rsk7269.h
> @@ -0,0 +1,76 @@
> +/*
> + * Configuation settings for the Renesas RSK2+SH7269 board
> + *
> + * Copyright (C) 2012 Renesas Electronics Europe Ltd.
> + * Copyright (C) 2012 Phil Edworthy
> + *
> + * This file is released under the terms of GPL v2 and any later version.
> + * See the file COPYING in the root directory of the source tree for details.
> + */
> +
> +#ifndef __RSK7269_H
> +#define __RSK7269_H
> +
> +#undef DEBUG
> +#define CONFIG_SH 1
> +#define CONFIG_SH2 1
> +#define CONFIG_SH2A 1
> +#define CONFIG_CPU_SH7269 1
> +#define CONFIG_RSK7269 1
> +
> +#ifndef _CONFIG_CMD_DEFAULT_H
> +# include <config_cmd_default.h>
> +#endif
> +
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_BOOTARGS "console=ttySC7,115200"
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
> +
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
> +#define CONFIG_SYS_CBSIZE 256 /* Boot Argument Buffer Size */
> +#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +
> +/* Serial */
> +#define CONFIG_SCIF_CONSOLE
> +#define CONFIG_CONS_SCIF7
> +
> +/* Memory */
> +/* u-boot relocated to top 256KB of ram */
> +#define CONFIG_SYS_TEXT_BASE 0x0DFC0000
> +#define CONFIG_SYS_SDRAM_BASE 0x0C000000
> +#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
> +
> +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
> +#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
> +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
> +
> +/* NOR Flash */
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> +#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +#define CONFIG_SYS_MAX_FLASH_SECT 512
> +
> +#define CONFIG_ENV_IS_IN_FLASH 1
> +#define CONFIG_ENV_OFFSET (128 * 1024)
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
> +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
> +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> +
> +/* Board Clock */
> +#define CONFIG_SYS_CLK_FREQ 66125000
> +#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
> +#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
> +
> +/* Network interface */
> +#define CONFIG_SMC911X
> +#define CONFIG_SMC911X_16_BIT
> +#define CONFIG_SMC911X_BASE 0x24000000
> +
> +#endif /* __RSK7269_H */
> --
> 1.7.5.4
>
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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