[U-Boot] [PATCH] arm: Tegra: Use ODMDATA from BCT in IRAM
Tom Warren
twarren.nvidia at gmail.com
Wed May 30 23:15:01 CEST 2012
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: Tom Warren <twarren at nvidia.com>
---
arch/arm/cpu/armv7/tegra2/ap20.c | 22 +++++++++++++++++++++-
arch/arm/include/asm/arch-tegra2/tegra2.h | 4 ++++
include/configs/harmony.h | 1 -
include/configs/medcom.h | 1 -
include/configs/paz00.h | 1 -
include/configs/plutux.h | 1 -
include/configs/seaboard.h | 1 -
include/configs/trimslice.h | 1 -
include/configs/ventana.h | 1 -
include/configs/whistler.h | 1 -
10 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index 24e582d..1aad387 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -314,9 +314,28 @@ void enable_scu(void)
writel(reg, &scu->scu_ctrl);
}
+static u32 get_odmdata(void)
+{
+ /*
+ * ODMDATA is stored in the BCT in IRAM by the BootROM.
+ * The BCT start and size are stored in the BIT in IRAM.
+ * Read the data @ bct_start + (bct_size - 12). This works
+ * on T20 and T30 BCTs, which are locked down. If this changes
+ * in new chips (T114, etc.), we can revisit this algorithm.
+ */
+
+ u32 bct_start, odmdata;
+
+ bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+ odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
+
+ return odmdata;
+}
+
void init_pmc_scratch(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ u32 odmdata;
int i;
/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
@@ -324,7 +343,8 @@ void init_pmc_scratch(void)
writel(0, &pmc->pmc_scratch1+i);
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
- writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
+ odmdata = get_odmdata();
+ writel(odmdata, &pmc->pmc_scratch20);
#ifdef CONFIG_TEGRA2_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index d4ada10..3c8d8a8 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -60,6 +60,10 @@ struct timerus {
/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
#define AP20_WB_RUN_ADDRESS 0x40020000
+#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
+#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
+
/* These are the available SKUs (product types) for Tegra */
enum {
SKU_ID_T20 = 0x8,
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d13ead9..df5265a 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -48,7 +48,6 @@
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
-#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/medcom.h b/include/configs/medcom.h
index d3d1055..bdea7c9 100644
--- a/include/configs/medcom.h
+++ b/include/configs/medcom.h
@@ -31,7 +31,6 @@
/* High-level configuration options */
#define V_PROMPT "Tegra2 (Medcom) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom"
-#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 29c368a..0dd1e83 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -35,7 +35,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
-#define CONFIG_SYS_BOARD_ODMDATA 0x800c0085 /* lp1, 512MB */
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index e73be0b..6397eb1 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -31,7 +31,6 @@
/* High-level configuration options */
#define V_PROMPT "Tegra2 (Plutux) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux"
-#define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 537ab0e..f661583 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -53,7 +53,6 @@
#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
-#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 915b07a..91de348 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -43,7 +43,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
-#define CONFIG_SYS_BOARD_ODMDATA 0x300c0011 /* lp?, 1GB, UARTA */
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 77a0a14..5e4d538 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -42,7 +42,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
-#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 9dafe5c..f2952d5 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -43,7 +43,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
-#define CONFIG_SYS_BOARD_ODMDATA 0x2B080105 /* lp?, 512MB, UARTA */
#define CONFIG_BOARD_EARLY_INIT_F
--
1.7.0.4
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