[U-Boot] [PATCH V3 20/32] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset
Troy Kisky
troy.kisky at boundarydevices.com
Thu Oct 4 03:47:22 CEST 2012
Bits 19-18 of IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
should be 3 for DDR3 mode. The current value of 0 is
reserved in TRM.
Signed-off-by: Troy Kisky <troy.kisky at boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index b859e2f..9c622c8 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -72,7 +72,7 @@ WRITE_ENTRY1(IOM_DRAM_RAS, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
-WRITE_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
WRITE_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
WRITE_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
--
1.7.9.5
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