[U-Boot] [PATCH v2] ARM: Add X600 board support (SPEAr600 based)
Albert ARIBAUD
albert.u.boot at aribaud.net
Thu Oct 4 10:22:06 CEST 2012
Hi Stefan,
On Thu, 31 May 2012 10:59:08 +0200, Stefan Roese <sr at denx.de> wrote:
> This patch adds support for the X600 SPEAr600 based board. Its also
> the first SPEAr600 board that uses the newly introduced SPEAr600
> SPL support. Xloader is not necessary any more. By using the new
> "u-boot.spr" make target, one image will generated containing both,
> U-Boot SPL (with mkimage header as needed by the SPEAr BootROM, and
> the main U-Boot with mkimage header.
>
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Amit Virdi <amit.virdi at st.com>
> Cc: Vipin Kumar <vipin.kumar at st.com>
> ---
> v2:
> - Add hush support
> - Add bootcount & altbootcmd support
>
> MAINTAINERS | 2 +
> board/spear/x600/Makefile | 47 +++++++
> board/spear/x600/fpga.c | 280 +++++++++++++++++++++++++++++++++++++
> board/spear/x600/fpga.h | 23 +++
> board/spear/x600/x600.c | 124 +++++++++++++++++
> boards.cfg | 1 +
> include/configs/x600.h | 339 +++++++++++++++++++++++++++++++++++++++++++++
> 7 files changed, 816 insertions(+)
> create mode 100644 board/spear/x600/Makefile
> create mode 100644 board/spear/x600/fpga.c
> create mode 100644 board/spear/x600/fpga.h
> create mode 100644 board/spear/x600/x600.c
> create mode 100644 include/configs/x600.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f796872..c55faff 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -828,6 +828,8 @@ John Rigby <jcrigby at gmail.com>
>
> Stefan Roese <sr at denx.de>
>
> + x600 ARM926EJS (spear600 Soc)
> +
> pdnb3 xscale/ixp
> scpu xscale/ixp
>
> diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
> new file mode 100644
> index 0000000..8c4e7e2
> --- /dev/null
> +++ b/board/spear/x600/Makefile
> @@ -0,0 +1,47 @@
> +#
> +# (C) Copyright 2000-2004
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +ifndef CONFIG_SPL_BUILD
> +COBJS := fpga.o $(BOARD).o
> +endif
> +SOBJS :=
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
> new file mode 100644
> index 0000000..85eb31b
> --- /dev/null
> +++ b/board/spear/x600/fpga.c
> @@ -0,0 +1,280 @@
> +/*
> + * Copyright (C) 2012 Stefan Roese <sr at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <spartan3.h>
> +#include <command.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/spr_misc.h>
> +#include <asm/arch/spr_ssp.h>
> +
> +/*
> + * FPGA program pin configuration on X600:
> + *
> + * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
> + * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
> + * 16bit serial writes via this SSP port to write the data bits into the
> + * FPGA.
> + */
> +#define CONFIG_SYS_FPGA_PROG 2
> +#define CONFIG_SYS_FPGA_DONE 3
> +
> +/*
> + * Set the active-low FPGA reset signal.
> + */
> +static void fpga_reset(int assert)
> +{
> + /*
> + * On x600 we have no means to toggle the FPGA reset signal
> + */
> + debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
> +}
> +
> +/*
> + * Set the FPGA's active-low SelectMap program line to the specified level
> + */
> +static int fpga_pgm_fn(int assert, int flush, int cookie)
> +{
> + debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
> +
> + gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
> +
> + return assert;
> +}
> +
> +/*
> + * Test the state of the active-low FPGA INIT line. Return 1 on INIT
> + * asserted (low).
> + */
> +static int fpga_init_fn(int cookie)
> +{
> + static int state;
> +
> + debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
> +
> + /*
> + * On x600, the FPGA INIT signal is not connected to the SoC.
> + * We can't read the INIT status. Let's return the "correct"
> + * INIT signal state generated via a local state-machine.
> + */
> + if (++state == 1) {
> + return 1;
> + } else {
> + state = 0;
> + return 0;
> + }
> +}
> +
> +/*
> + * Test the state of the active-high FPGA DONE pin
> + */
> +static int fpga_done_fn(int cookie)
> +{
> + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
> +
> + /*
> + * Wait for Tx-FIFO to become empty before looking for DONE
> + */
> + while (!(readl(&ssp->sspsr) & SSPSR_TFE))
> + ;
> +
> + if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
> + return 1;
> + else
> + return 0;
> +}
> +
> +/*
> + * FPGA pre-configuration function. Just make sure that
> + * FPGA reset is asserted to keep the FPGA from starting up after
> + * configuration.
> + */
> +static int fpga_pre_config_fn(int cookie)
> +{
> + debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
> + fpga_reset(TRUE);
> +
> + return 0;
> +}
> +
> +/*
> + * FPGA post configuration function. Blip the FPGA reset line and then see if
> + * the FPGA appears to be running.
> + */
> +static int fpga_post_config_fn(int cookie)
> +{
> + int rc = 0;
> +
> + debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
> +
> + fpga_reset(TRUE);
> + udelay(100);
> + fpga_reset(FALSE);
> + udelay(100);
> +
> + return rc;
> +}
> +
> +static int fpga_clk_fn(int assert_clk, int flush, int cookie)
> +{
> + /*
> + * No dedicated clock signal on x600 (data & clock generated)
> + * in SSP interface. So we don't have to do anything here.
> + */
> + return assert_clk;
> +}
> +
> +static int fpga_wr_fn(int assert_write, int flush, int cookie)
> +{
> + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
> + static int count;
> + static u16 data;
> +
> + /*
> + * First collect 16 bits of data
> + */
> + data = data << 1;
> + if (assert_write)
> + data |= 1;
> +
> + /*
> + * If 16 bits are not available, return for more bits
> + */
> + count++;
> + if (count != 16)
> + return assert_write;
> +
> + count = 0;
> +
> + /*
> + * Wait for Tx-FIFO to become ready
> + */
> + while (!(readl(&ssp->sspsr) & SSPSR_TNF))
> + ;
> +
> + /* Send 16 bits to FPGA via SSP bus */
> + writel(data, &ssp->sspdr);
> +
> + return assert_write;
> +}
> +
> +static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
> + fpga_pre_config_fn,
> + fpga_pgm_fn,
> + fpga_clk_fn,
> + fpga_init_fn,
> + fpga_done_fn,
> + fpga_wr_fn,
> + fpga_post_config_fn,
> +};
> +
> +static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
> + XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
> +};
> +
> +/*
> + * Initialize the SelectMap interface. We assume that the mode and the
> + * initial state of all of the port pins have already been set!
> + */
> +static void fpga_serialslave_init(void)
> +{
> + debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
> + fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
> +}
> +
> +static int expi_setup(int freq)
> +{
> + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
> + int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
> +
> + pll2_m = (freq * 2) / 1000;
> + pll2_n = 15;
> + pll2_p = 1;
> + expi_x = 1;
> + expi_y = 2;
> +
> + /*
> + * Disable reset, Low compression, Disable retiming, Enable Expi,
> + * Enable soft reset, DMA, PLL2, Internal
> + */
> + writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
> + EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
> + EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
> + &misc->expi_clk_cfg);
> +
> + /*
> + * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
> + * Enable PLL2, Disable reset
> + */
> + writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
> + writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
> + PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
> +
> + /*
> + * Disable soft reset
> + */
> + clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
> +
> + return 0;
> +}
> +
> +/*
> + * Initialize the fpga
> + */
> +int x600_init_fpga(void)
> +{
> + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
> + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
> +
> + /* Enable SSP2 clock */
> + writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
> + &misc->periph1_clken);
> +
> + /* Set EXPI clock to 45 MHz */
> + expi_setup(45000);
> +
> + /* Configure GPIO directions */
> + gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
> + gpio_direction_input(CONFIG_SYS_FPGA_DONE);
> +
> + writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
> + writel(SSPCR1_SSE, &ssp->sspcr1);
> +
> + /*
> + * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
> + * speed.
> + *
> + * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
> + * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
> + */
> + writel(2, &ssp->sspcpsr);
> +
> + fpga_init();
> + fpga_serialslave_init();
> +
> + debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
> + fpga_add(fpga_xilinx, &fpga[0]);
> +
> + return 0;
> +}
> diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h
> new file mode 100644
> index 0000000..2b18557
> --- /dev/null
> +++ b/board/spear/x600/fpga.h
> @@ -0,0 +1,23 @@
> +/*
> + * Copyright (C) 2012 Stefan Roese <sr at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +int x600_init_fpga(void);
> diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
> new file mode 100644
> index 0000000..96ec0ad
> --- /dev/null
> +++ b/board/spear/x600/x600.c
> @@ -0,0 +1,124 @@
> +/*
> + * (C) Copyright 2009
> + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
> + *
> + * Copyright (C) 2012 Stefan Roese <sr at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <nand.h>
> +#include <netdev.h>
> +#include <phy.h>
> +#include <rtc.h>
> +#include <asm/io.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/spr_defs.h>
> +#include <asm/arch/spr_misc.h>
> +#include <linux/mtd/fsmc_nand.h>
> +#include "fpga.h"
> +
> +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
> +
> +int board_init(void)
> +{
> + /*
> + * X600 is equipped with an M41T82 RTC. This RTC has the
> + * HT bit (Halt Update), which needs to be cleared upon
> + * power-up. Otherwise the RTC is halted.
> + */
> + rtc_reset();
> +
> + return spear_board_init(MACH_TYPE_SPEAR600);
> +}
> +
> +int board_late_init(void)
> +{
> + /*
> + * Monitor and env protection on by default
> + */
> + flash_protect(FLAG_PROTECT_SET,
> + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
> + CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
> + 2 * CONFIG_ENV_SECT_SIZE - 1,
> + &flash_info[0]);
> +
> + /* Init FPGA subsystem */
> + x600_init_fpga();
> +
> + return 0;
> +}
> +
> +/*
> + * board_nand_init - Board specific NAND initialization
> + * @nand: mtd private chip structure
> + *
> + * Called by nand_init_chip to initialize the board specific functions
> + */
> +
> +void board_nand_init(void)
> +{
> + struct misc_regs *const misc_regs_p =
> + (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
> + struct nand_chip *nand = &nand_chip[0];
> +
> + if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
> + fsmc_nand_init(nand);
> +}
> +
> +int designware_board_phy_init(struct eth_device *dev, int phy_addr,
> + int (*mii_write)(struct eth_device *, u8, u8, u16),
> + int dw_reset_phy(struct eth_device *))
> +{
> + /* Extended PHY control 1, select GMII */
> + mii_write(dev, phy_addr, 23, 0x0020);
> +
> + /* Software reset necessary after GMII mode selction */
> + dw_reset_phy(dev);
> +
> + /* Enable extended page register access */
> + mii_write(dev, phy_addr, 31, 0x0001);
> +
> + /* 17e: Enhanced LED behavior, needs to be written twice */
> + mii_write(dev, phy_addr, 17, 0x09ff);
> + mii_write(dev, phy_addr, 17, 0x09ff);
> +
> + /* 16e: Enhanced LED method select */
> + mii_write(dev, phy_addr, 16, 0xe0ea);
> +
> + /* Disable extended page register access */
> + mii_write(dev, phy_addr, 31, 0x0000);
> +
> + /* Enable clock output pin */
> + mii_write(dev, phy_addr, 18, 0x0049);
> +
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int ret = 0;
> +
> + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
> + PHY_INTERFACE_MODE_GMII) >= 0)
> + ret++;
> +
> + return ret;
> +}
> diff --git a/boards.cfg b/boards.cfg
> index 2a75880..89984d0 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -193,6 +193,7 @@ spear600 arm arm926ejs spear600 spear
> spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand
> spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty
> spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand
> +x600 arm arm926ejs - spear spear x600
> versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
> versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
> versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
> diff --git a/include/configs/x600.h b/include/configs/x600.h
> new file mode 100644
> index 0000000..3082aaa
> --- /dev/null
> +++ b/include/configs/x600.h
> @@ -0,0 +1,339 @@
> +/*
> + * (C) Copyright 2009
> + * Vipin Kumar, STMicroelectronics, <vipin.kumar at st.com>
> + *
> + * Copyright (C) 2012 Stefan Roese <sr at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * High Level Configuration Options
> + * (easy to change)
> + */
> +#define CONFIG_SPEAR600 /* SPEAr600 SoC */
> +#define CONFIG_X600 /* on X600 board */
> +
> +#include <asm/arch/hardware.h>
> +
> +/* Timer, HZ specific defines */
> +#define CONFIG_SYS_HZ 1000
> +#define CONFIG_SYS_HZ_CLOCK 8300000
> +
> +#define CONFIG_SYS_TEXT_BASE 0x00800040
> +#define CONFIG_SYS_FLASH_BASE 0xf8000000
> +/* Reserve 8KiB for SPL */
> +#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
> +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
> +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
> + CONFIG_SYS_SPL_LEN)
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
> +#define CONFIG_SYS_MONITOR_LEN 0x60000
> +
> +#define CONFIG_ENV_IS_IN_FLASH
> +
> +/* Serial Configuration (PL011) */
> +#define CONFIG_SYS_SERIAL0 0xD0000000
> +#define CONFIG_SYS_SERIAL1 0xD0080000
> +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
> + (void *)CONFIG_SYS_SERIAL1 }
> +#define CONFIG_PL011_SERIAL
> +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
> +#define CONFIG_CONS_INDEX 0
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
> + 57600, 115200 }
> +#define CONFIG_SYS_LOADS_BAUD_CHANGE
> +
> +/* NOR FLASH config options */
> +#define CONFIG_ST_SMI
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
> +#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
> +#define CONFIG_SYS_MAX_FLASH_SECT 128
> +#define CONFIG_SYS_FLASH_EMPTY_INFO
> +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
> +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
> +
> +/* NAND FLASH config options */
> +#define CONFIG_NAND_FSMC
> +#define CONFIG_SYS_NAND_SELF_INIT
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
> +#define CONFIG_MTD_ECC_SOFT
> +#define CONFIG_SYS_FSMC_NAND_8BIT
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +
> +/* UBI/UBI config options */
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_MTD_PARTITIONS
> +#define CONFIG_RBTREE
> +
> +/* Ethernet config options */
> +#define CONFIG_MII
> +#define CONFIG_DESIGNWARE_ETH
> +#define CONFIG_DW_SEARCH_PHY
> +#define CONFIG_NET_MULTI
> +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
> +#define CONFIG_DW_AUTONEG
> +#define CONFIG_PHY_ADDR 0 /* PHY address */
> +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
> +
> +#define CONFIG_SPEAR_GPIO
> +
> +/* I2C config options */
> +#define CONFIG_HARD_I2C
> +#define CONFIG_DW_I2C
> +#define CONFIG_SYS_I2C_SPEED 400000
> +#define CONFIG_SYS_I2C_SLAVE 0x02
> +#define CONFIG_I2C_CHIPADDRESS 0x50
> +
> +#define CONFIG_RTC_M41T62 1
> +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
> +
> +/* FPGA config options */
> +#define CONFIG_FPGA
> +#define CONFIG_FPGA_XILINX
> +#define CONFIG_FPGA_SPARTAN3
> +#define CONFIG_FPGA_COUNT 1
> +
> +/*
> + * Command support defines
> + */
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_ENV
> +#define CONFIG_CMD_FPGA
> +#define CONFIG_CMD_GPIO
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_MEMORY
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_RUN
> +#define CONFIG_CMD_SAVES
> +#define CONFIG_CMD_UBI
> +#define CONFIG_CMD_UBIFS
> +#define CONFIG_LZO
> +
> +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +
> +/*
> + * U-Boot Environment placing definitions.
> + */
> +#define CONFIG_ENV_SECT_SIZE 0x00010000
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
> + CONFIG_SYS_MONITOR_LEN)
> +#define CONFIG_ENV_SIZE 0x02000
> +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
> + CONFIG_ENV_SECT_SIZE)
> +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_ARCH_CPU_INIT
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_MISC_INIT_R
> +#define CONFIG_BOARD_LATE_INIT
> +#define CONFIG_LOOPW /* enable loopw command */
> +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
> +#define CONFIG_ZERO_BOOTDELAY_CHECK
> +#define CONFIG_AUTOBOOT_KEYED
> +#define CONFIG_AUTOBOOT_STOP_STR " "
> +#define CONFIG_AUTOBOOT_PROMPT \
> + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
> +
> +#define CONFIG_SYS_MEMTEST_START 0x00800000
> +#define CONFIG_SYS_MEMTEST_END 0x04000000
> +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
> +#define CONFIG_IDENT_STRING "-SPEAr"
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_SYS_PROMPT "X600> "
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_LOAD_ADDR 0x00800000
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET
> +#define CONFIG_SYS_64BIT_VSPRINTF
> +
> +/* Use last 2 lwords in internal SRAM for bootcounter */
> +#define CONFIG_BOOTCOUNT_LIMIT
> +#define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8
> +
> +#define CONFIG_HOSTNAME x600
> +#define CONFIG_UBI_PART ubi0
> +#define CONFIG_UBIFS_VOLUME rootfs
> +
> +#define xstr(s) str(s)
> +#define str(s) #s
> +
> +#define MTDIDS_DEFAULT "nand0=nand"
> +#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "u-boot_addr=1000000\0" \
> + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \
> + "load=tftp ${u-boot_addr} ${u-boot}\0" \
> + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\
> + "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
> + "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \
> + " ${filesize};" \
> + "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \
> + " +${filesize}\0" \
> + "upd=run load update\0" \
> + "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \
> + "part=" xstr(CONFIG_UBI_PART) "\0" \
> + "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \
> + "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
> + "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
> + " ${filesize}\0" \
> + "upd_ubifs=run load_ubifs update_ubifs\0" \
> + "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
> + "ubi create ${vol} 4000000\0" \
> + "netdev=eth0\0" \
> + "rootpath=/opt/eldk-4.2/arm\0" \
> + "nfsargs=setenv bootargs root=/dev/nfs rw " \
> + "nfsroot=${serverip}:${rootpath}\0" \
> + "ramargs=setenv bootargs root=/dev/ram rw\0" \
> + "boot_part=0\0" \
> + "altbootcmd=if test $boot_part -eq 0;then " \
> + "echo Switching to partition 1!;" \
> + "setenv boot_part 1;" \
> + "else; " \
> + "echo Switching to partition 0!;" \
> + "setenv boot_part 0;" \
> + "fi;" \
> + "saveenv;boot\0" \
> + "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
> + "root=ubi0:rootfs rootfstype=ubifs\0" \
> + "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
> + "kernel_fs=/boot/uImage \0" \
> + "kernel_addr=1000000\0" \
> + "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
> + "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
> + "dtb_addr=1800000\0" \
> + "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
> + "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
> + "addip=setenv bootargs ${bootargs} " \
> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> + ":${hostname}:${netdev}:off panic=1\0" \
> + "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
> + "${baudrate}\0" \
> + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
> + "net_nfs=run load_dtb load_kernel; " \
> + "run nfsargs addip addcon addmtd addmisc;" \
> + "bootm ${kernel_addr} - ${dtb_addr}\0" \
> + "mtdids=" MTDIDS_DEFAULT "\0" \
> + "mtdparts=" MTDPARTS_DEFAULT "\0" \
> + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
> + " addcon addmisc addmtd;" \
> + "bootm ${kernel_addr} - ${dtb_addr}\0" \
> + "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \
> + "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
> + "ubifsload ${dtb_addr} ${dtb_fs};\0" \
> + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
> + "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
> + "bootcmd=run nand_ubifs\0" \
> + "\0"
> +
> +/* Stack sizes */
> +#define CONFIG_STACKSIZE (512 * 1024)
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM_1 0x00000000
> +#define PHYS_SDRAM_1_MAXSIZE 0x40000000
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> +#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/*
> + * SPL related defines
> + */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_TEXT_BASE 0xd2800b00
> +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
> +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
> +
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
> +#define CONFIG_SPL_NO_PRINTF
> +
> +/*
> + * Please select/define only one of the following
> + * Each definition corresponds to a supported DDR chip.
> + * DDR configuration is based on the following selection
> + */
> +#define CONFIG_DDR_MT47H64M16 1
> +#define CONFIG_DDR_MT47H32M16 0
> +#define CONFIG_DDR_MT47H128M8 0
> +
> +/*
> + * Synchronous/Asynchronous operation of DDR
> + *
> + * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
> + * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
> + * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
> + */
> +#define CONFIG_DDR_2HCLK 1
> +#define CONFIG_DDR_HCLK 0
> +#define CONFIG_DDR_PLL2 0
> +
> +/*
> + * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
> + * or not. Modify/Add to only these macros to define new boot types
> + */
> +#define USB_BOOT_SUPPORTED 0
> +#define PCIE_BOOT_SUPPORTED 0
> +#define SNOR_BOOT_SUPPORTED 1
> +#define NAND_BOOT_SUPPORTED 1
> +#define PNOR_BOOT_SUPPORTED 0
> +#define TFTP_BOOT_SUPPORTED 0
> +#define UART_BOOT_SUPPORTED 0
> +#define SPI_BOOT_SUPPORTED 0
> +#define I2C_BOOT_SUPPORTED 0
> +#define MMC_BOOT_SUPPORTED 0
> +
> +#endif /* __CONFIG_H */
Applied to u-boot-arm/master, thanks!
Amicalement,
--
Albert.
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