[U-Boot] [PATCH 07/11] arm: ks8695/cm4008/cm41xx: Parameterize SDRAM

[Yann Vernier]

Allows configuration macros to set SDRAM parameters.
---
 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S |   20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
index 74579ed..bec9738 100644
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
@@ -157,19 +157,20 @@ highflash:
 	/*
 	 * before relocating, we have to setup RAM timing
 	 */
+#if CONFIG_SYS_SDCS0_PARAMS
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
-	ldr	r2, =0x7fc0000e		/* 32MB */
-#else
-	ldr	r2, =0x3fc0000e		/* 16MB */
-#endif
+	ldr	r2, =CONFIG_KS8695_SDCON0_VALUE
 	str	r2, [r1]		/* configure sdram bank0 setup */
+#endif
+#if CONFIG_SYS_SDCS1_PARAMS
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
-	mov	r2, #0
+	mov	r2, #CONFIG_KS8695_SDCON1_VALUE
 	str	r2, [r1]		/* configure sdram bank1 setup */
+#endif
 
+#if CONFIG_SYS_SDCS0_PARAMS || CONFIG_SYS_SDCS1_PARAMS
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
-	ldr	r2, =0x0000000a
+	ldr	r2, =CONFIG_KS8695_SDGCON_VALUE
 	str	r2, [r1]		/* set RAS/CAS timing */
 
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
@@ -184,15 +185,16 @@ highflash:
 	ldr	r2, =0x00000020
 	str	r2, [r1]		/* set for fast refresh */
 	DELAY_FOR 0x100, r0
-	ldr	r2, =0x00000190
+	ldr	r2, =CONFIG_SYS_SDRAM_REFRESH_RATE
 	str	r2, [r1]		/* set normal refresh timing */
 
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
-	ldr	r2, =0x00020033
+	ldr	r2, =(0x00020000 | CONFIG_SYS_SDRAM_MODE)
 	str	r2, [r1]		/* send mode command */
 	DELAY_FOR 0x100, r0
 	ldr	r2, =0x01f00000
 	str	r2, [r1]		/* enable sdram fifos */
+#endif
 
 	/*
 	 * set pll to top speed
-- 
1.7.10.4